AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 122

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

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MIIPDTINT
MCCIINTE PHY Management Command
MIIPDTINT PHY Detect Transition Interrupt.
When MCCIINT is set to 1,
INTA is asserted if the enable
bit MCCINTE is set to 1.
This bit is always read/write ac-
cessible. MCCIINT is cleared by
the host by writing a 1. Writing a
0 has no effect. MCCIINT is
cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
This bit is always read/write ac-
cessible. MCCIINTE is set to 0
by H_RESET and is not affected
by S_RESET or setting the
STOP bit.
This bit is always read/write ac-
cessible. MIIPDTINT is cleared
by the host by writing a 1. Writing
a 0 has no effect. MIIPDTINT is
cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
This bit is always read/write ac-
cessible. MIIPDTINTE is set to 0
by H_RESET and is not affected
by S_RESET or setting the
STOP bit.
Complete Internal Interrupt En-
able. If MCCIINTE is set to 1, the
MCCIINT bit will be able to set
the INTR bit when the internal
state machines generate man-
agement frames. For instance,
when MCCIINTE is set to 1 and
the Auto-Poll state machine gen-
erates a management frame, the
MCCIINT will set the INTR bit
upon completion of the manage-
ment frame regardless of the
comparison outcome.
The PHY Detect Transition Inter-
rupt is set by the Am79C978A
controller whenever the MIIPD bit
(BCR32, bit 14) transitions from 0
to 1 or vice versa.
PHY Detect Transition Interrupt
Enable. If MIIPDTINTE is set to 1,
the MIIPDTINT bit will be able to
set the INTR bit.
Am79C978A
CSR8: Logical Address Filter 0
Bit
31-16 RES
15-0
CSR9: Logical Address Filter 1
Bit
31-16 RES
15-0 LADRF[31:16]Logical
CSR10: Logical Address Filter 2
Bit
31-16 RES
15-0 LADRF[47:32]Logical
LADRF[15:0] Logical Address Filter, LADRF-
Name
Name
Name
zeros and read as undefined.
[15:0]. The content of this register
is undefined until loaded from the
initialization block after the INIT
bit in CSR0 has been set or a di-
rect register write has been per-
formed on this register.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
LADRF-[31:16]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct regis-
ter write has been performed
on this register.
These bits are These bits are
read/write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on
this register.
Description
Reserved locations. Written as
Description
Reserved locations. Written as
Description
Reserved locations. Written as
Address
Address
Filter,
Filter,