AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 169

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

3
2
1
0
BCR33: PHY Address Register
Bit
31-16 RES
15
XPHYSP
RES
MIIILP
RES
SHADOW
Name
This bit is always read/write ac-
cessible. XPHYFD is set to 0 by
H_RESET, and is unaffected by
S_RESET and the STOP bit.
PHY Speed. When set, this bit
will force the PHY into 100 Mbps
mode when Auto-Negotiation is
not enabled.
This bit is always read/write ac-
cessible. XPHYSP is set to 0 by
H_RESET, and is unaffected by
S_RESET and the STOP bit.
Reserved location. Written as
zero and read as undefined.
Media Independent Interface In-
ternal Loopback. When set, this
bit will cause the internal portion
of the MII data port to loopback
on itself. The interface is mapped
in
TXD[3:0] nibble data path is
looped back onto the RXD[3:0]
nibble data path. TX_CLK is
looped back as RX_CLK. TX_EN
is looped back as RX_DV. CRS is
correctly OR’d with TX_EN and
RX_DV and always encompass-
es the transmit frame. TX_ER is
looped back as RX_ER. Howev-
er, TX_ER will not get asserted
by the Am79C978A controller to
signal an error. The TX_ER func-
tion is reserved for future use.
This bit is always read/write ac-
cessible. MIIILP is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
Reserved location. Written as
zero and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
If the user wishes to update
the contents of the BCR33
shadow register, setting the
MSB of the value written into
BCR33 (bit 15) will enable the
Description
the
following
way.
Am79C978A
The
9-5
4-0
BCR34: PHY Management Data Register
Bit
31-16 RES
15-0
PHYAD
REGAD
MIIMD
Name
Reserved locations. Written as
contents to be simultaneously
written to BCR33 shadow.
Management Frame PHY Ad-
dress. PHYAD contains the 5-bit
PHY Address field that is used in
the management frame that gets
clocked out via the MII manage-
ment port pins (MDC and MDIO)
whenever a read or write transac-
tion occurs to BCR34. The PHY
address 1Fh is not valid.
The Network Port Manager cop-
ies
Am79C978A controller reads the
EEPROM and uses it to commu-
nicate with the external PHY.
The PHY address must be pro-
grammed into the EEPROM pri-
or to starting the Am79C978A
controller.
These bits are always read/write
accessible. PHYAD is undefined
after H_RESET and is unaffected
by S_RESET and the STOP bit.
Management Frame Register
Address. REGAD contains the
5-bit Register Address field that
is used in the management
frame that gets clocked out via
the internal MII management in-
terface whenever a read or write
transaction occurs to BCR34.
These bits are always read/write
accessible. REGAD is undefined
after H_RESET and is unaffected
by S_RESET and the STOP bit.
zeros and read as undefined.
MII Management Data. MIIMD is
the data port for operations on
the MII management interface
(MDIO
Am79C978A controller builds
management frames using the
PHYAD and REGAD values
from BCR33. The operation
code used in each frame is
based upon whether a read or
Description
the
and
PHYAD
MDC).
after
169
The
the