AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 121

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

8
7
6
MREINTE
MAPINT
MAPINTE
When MREINT is set to 1, INTA is
asserted
MREINTE is set to 1.
This bit is always read/write acces-
sible. MREINT is cleared by the
host by writing a 1. Writing a 0 has
no effect. MREINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP bit.
This bit is always read/write ac-
cessible. MREINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP bit
When MAPINT is set to 1, INTA is
asserted
MAPINTE is set to 1.
This bit is always read/write acces-
sible. MAPINT is cleared by the
host by writing a 1. Writing a 0 has
no effect. MAPINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP bit.
This bit is always read/write acces-
sible. MAPINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP bit.
PHY Management Read Error In-
terrupt Enable. If MREINTE is
set, the MREINT bit will be able to
set the INTR bit.
PHY Management Auto-Poll In-
terrupt. The PHY Auto-Poll inter-
rupt is set by the Am79C978A
controller to indicate that the cur-
rently read status does not match
the stored previous status indi-
cating a change in state for the in-
ternal PHY. A change in the Auto-
Poll Access Method (BCR32, Bit
11) will reset the shadow register
and will not cause an interrupt on
the first access from the Auto-Poll
section. Subsequent accesses
will generate an interrupt if the
shadow register and the read
register produce differences.
PHY Auto-Poll Interrupt Enable.
If MAPINTE is set, the MAPINT
bit will be able to set the INTR bit.
if
if
the
the
enable
enable
Am79C978A
bit
bit
5
4
3
MCCINT
MCCINTE
MCCIINT
Complete Interrupt. The PHY
Management Command Com-
plete Interrupt is set by the
Am79C978A controller when a
read or write operation to the in-
ternal PHY Data Port (BCR34) is
complete.
When MCCINT is set to 1, INTA
is asserted if the enable bit
MCCINTE is set to 1.
This bit is always read/write ac-
cessible. MCCINT is cleared by
the host by writing a 1. Writing a
0 has no effect. MCCINT is
cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
Complete Interrupt Enable. If
MCCINTE is set to 1, the
MCCINT bit will be able to set the
INTR bit when the host reads or
writes to the internal PHY Data
Port (BCR34) only. Internal PHY
Management Commands will not
generate an interrupt. For in-
stance Auto-Poll state machine
generated management frames
will not generate an interrupt
upon completion unless there is a
compare error which gets report-
ed through the MAPINT (CSR7,
bit 6) interrupt or the MCCIINTE
is set to 1.
This bit is always read/write ac-
cessible. MCCINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP bit.
Complete Internal Interrupt. The
PHY
Complete Interrupt is set by the
Am79C978A controller when a
read or write operation on the in-
ternal PHY management port is
complete from an internal opera-
tion. Examples of internal opera-
tions are Auto-Poll or PHY
Management
management frames. These are
normally hidden to the host.
PHY Management Command
PHY Management Command
PHY Management Command
Management
Port
Command
generated
121