AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 123

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR11: Logical Address Filter 3
Bit
31-16
15-0 LADRF[63:48]Logical
CSR12: Physical Address Register 0
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16
15-0
Name
RES
Name
RES
PADR[15:0] Physical
These bit are read/write accessi-
ble only when either the STOP or
the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
Description
Reserved locations. Written as
zeros and read as undefined.
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
Description
Reserved locations. Written as
zeros and read as undefined.
PADR[15:0]. The contents of this
register are loaded from the
EEPROM after H_RESET or by
an EEPROM read command
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the
contents of this register are un-
defined.
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Address
Address
Register,
Filter,
Am79C978A
CSR13: Physical Address Register 1
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15-0
CSR14: Physical Address Register 2
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15-0
PADR[31:16]Physical
PADR[47:32]Physical
Name
Name
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
PADR[31:16]. The contents of
this register are loaded from the
EEPROM after H_RESET or by
an EEPROM read command
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the
contents of this register are un-
defined.
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
PADR[47:32]. The contents of
this register are loaded from
the EEPROM after H_RESET
or by an EEPROM read com-
mand (PRGAD, BCR19, bit 14).
If the EEPROM is not present,
the contents of this register are
undefined.
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Description
Reserved locations. Written as
This register can also be loaded
Description
Reserved locations. Written as
This register can also be loaded
Address
Address
Register,
Register,
123