AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 165

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

2-0
CLK_FAC
1XX
000
001
010
011
CLK_FAC
Table 44. CLK_FAC Values
Note: The clock frequency driv-
ing the Expansion Bus access cy-
cles that results from the settings
of the EBCS and CLK FAC bits
must not exceed 33 MHz at any
time. When EBCS is set to either
the PCI clock or the Time Base
clock, no external clock source is
required because the clocks are
routed internally and the EBCLK
pin should be pulled to VDD
through a resistor.
CAUTION: Care should be exer-
cised when choosing the PCI
clock pin because of the nature
of the PCI clock signal. The PCI
specification states that the PCI
clock can be stopped. If that can
occur while it is being used for
the Expansion Bus clock data,
corruption will result.
CAUTION:
Clock will not support 100 Mbps
operation and should only be
selected in 10 Mbps-only con-
figurations.
CAUTION: The external clock
source
EBCLK pin must be a continu-
ous clock source at all times.
Clock Factor. These bits are used
to select whether the clock select-
ed by EBCS is used directly or if it
is divided down to give a slower
clock for running the Expansion
Bus access cycles. The possible
factors are given in Table 44.
Read accessible always; write
accessible only when the STOP
bit is set. CLK_FAC is set to 000b
during H_RESET and is unaffect-
ed by S_RESET or STOP.
1/2 (divide by 2)
1/4 (divide by 4)
Clock Factor
Reserved
Reserved
used
1
The
to
Time
drive
Base
Am79C978A
the
BCR28: Expansion Bus Port Address Lower (Used
for Flash/EPROM and SRAM Accesses)
Bit
31-16 RES
15-0
BCR29: Expansion Port Address Upper (Used for
Flash/EPROM Accesses)
Bit
31-16 RES
15
EPADDRL
FLASH
Name
Name
Reserved locations. Written as
Expansion Port Address Lower.
Reserved locations. Written as
zeros and read as undefined.
This address is used to provide
addresses for the Flash and
SRAM port accesses.
SRAM accesses are started
when a read or write is performed
on BCR30 and the FLASH (BCR
29, bit 15) is set to 0. During
SRAM accesses only bits in the
EPADDRL are valid. Since all
SRAM accesses are word orient-
ed only, EPADDRL[0] is the least
significant word address bit. On
any byte write accesses to the
SRAM, the user will have to fol-
low
scheme. On any byte read ac-
cesses to the SRAM, the user will
have to chose which byte is
needed from the complete word
returned in BCR30.
Flash accesses are started when
a read or write is performed on
BCR30 and the FLASH (BCR 29,
bit 15) is set to 1. During Flash
accesses all bits in EPADDR are
valid.
Read accessible always; write
accessible only when the STOP
is set or when SRAM SIZE
(BCR25, bits 7-0) is 0. EPADDRL
is undefined after H_RESET and
is unaffected by S_RESET or
STOP.
zeros and read as undefined.
Flash Access. When the FLASH
bit is set to 1, the Expansion Bus
access will be a Flash cycle.
When FLASH is set to 0, the Ex-
pansion Bus access will be a
Description
Description
the
read-modify-write
165