AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 130

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR45: Next Receive Status
Bit
31-16 RESReserved locations. Written as zeros and
15-0
CSR46: Transmit Poll Time Counter
Bit
31-16 RES
15-0
CSR47: Transmit Polling Interval
Bit
31-16 RES
15-0 TXPOLLINT
130
NRSTNext Receive Status. This field is a copy
TXPOLL
Name
Name
Name
read as undefined.
of bits 31-16 of RMD1 of the next
receive descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
Transmit Poll Time Counter. This
counter is incremented by the
Am79C978A
code and is used to trigger the
transmit descriptor ring polling
operation of the Am79C978A
controller.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
Transmit Polling Interval. This
register contains the time that the
Am79C978A controller will wait
between successive polling oper-
ations. The TXPOLLINT value is
expressed as the two’s comple-
ment of the desired interval,
where each bit of TXPOLLINT
represents 1 clock period of time.
TXPOLLINT[3:0]
(TXPOLLINT[16] is implied to be
a one, so TXPOLLINT[15] is sig-
nificant and does not represent
the sign of the two’s complement
TXPOLLINT value.)
Description
Description
Description
Reserved locations. Written as
controller
are
ignored.
micro-
Am79C978A
CSR48: Receive Poll Time Counter
Bit
31-16 RES
15-0
RXPOLL
Name
Reserved locations. Written as
Receive Poll Time Counter. This
The default value of this reg-
ister is 0000h. This corre-
sponds to a polling interval of
65,536 clock periods (1.966
ms when CLK = 33 MHz).
The
0000h is created during the
microcode initialization rou-
tine and, therefore, might not
be seen when reading CSR47
after H_RESET or S_RESET.
If the user desires to program a
value for POLLINT other than
the default, then the correct pro-
cedure is to first set INIT only in
CSR0. Then, when the initializa-
tion sequence is complete, the
user must set STOP (CSR0, bit
2). Then the user may write to
CSR47 and then set STRT in
CSR0. In this way, the default
value of 0000h in CSR47 will be
overwritten with the desired
user value.
If the user does not use the
standard initialization procedure
(standard implies use of an ini-
tialization block in memory and
setting the INIT bit of CSR0),
but instead chooses to write di-
rectly to each of the registers
that are involved in the INIT op-
eration, then it is imperative that
the user also writes all zeros to
CSR47 as part of the alternative
initialization sequence.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
counter is incremented by the
Am79C978A controller microcode
and is used to trigger the receive
descriptor ring polling operation of
the Am79C978A controller.
Description
TXPOLLINT
value
of