AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 141

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR122: Advanced Feature Control
Bit
31-1
0
CSR124: Test Register 1
This register is used to place the Am79C978A controller
into various test modes. The Runt Packet Accept is the
only user accessible test mode. All other test modes are
for AMD internal use only.
Bit
31-4
3
2-0
RES
RCVALGN
RES
RPA
RES
Name
Name
Receive Packet Align. When set,
Reserved locations. Written as
zeros and read as undefined.
this bit forces the data field of ISO
8802-3 (IEEE/ANSI 802.3) pack-
ets to align to 0 MOD 4 address
boundaries (i.e., DWord aligned
addresses). It is important to note
that this feature will only function
correctly if all receive buffer
boundaries are DWord aligned
and all receive buffers have 0
MOD 4 lengths. In order to ac-
complish the data alignment, the
Am79C978A controller simply in-
serts two bytes of random data at
the beginning of the receive pack-
et (i.e., before the ISO 8802-3
(IEEE/ANSI 802.3) destination
address field). The MCNT field
reported to the receive descriptor
will not include the extra two
bytes.
This bit is always read/write ac-
cessible. RCVALGN is cleared by
H_RESET or S_RESET and is
not affected by STOP.
Reserved locations. Written as
zeros and read as undefined.
Runt Packet Accept. This bit
forces the Am79C978A controller
to accept runt packets (packets
shorter than 64 bytes).
This bit is read accessible al-
ways; write accessible only when
STOP is set to 1. RPA is cleared
by H_RESET or S_RESET and is
not affected by STOP.
Reserved locations. Written as
zeros and read as undefined.
Description
Description
Am79C978A
CSR125: MAC Enhanced Configuration Control
Bit
31-16 RES
15-8
IPG
Name
Note: Programming of the IPG
should be done in nibble intervals
instead of absolute bit times. The
decimal and hex values do not
match due to delays in the part
used to make up the final IPG.
Changes should be added or sub-
tracted from the provided hex value
on a one-for-one basis.
Reserved locations. Written as
zeros and read as undefined.
Inter Packet Gap. Changing IPG
allows the user to program the
Am79C978A controller for ag-
gressiveness on a network. By
changing the default value of 96
bit times (60h) the user can adjust
the fairness or aggressiveness of
the Am79C978A integrated MAC
on the network. By programming
a lower number of bit times other
then the ISO/IEC 8802-3 stan-
dard requires, the Am79C978A
controller will become more ag-
gressive on the network. This ag-
gressive nature will give rise to
the Am79C978A controller possi-
bly “capturing the network” at
times by forcing other less ag-
gressive nodes to defer. By pro-
gramming a larger number of bit
times, the Am79C978A home
networking MAC will become less
aggressive on the network and
may defer more often than nor-
mal. The performance of the
Am79C978A controller may de-
crease as the IPG value is in-
creased from the default value.
CAUTION: Use this parame-
ter with care. By lowering
the IPG below the ISO/IEC
8802-3 standard 96 bit times,
the Am79C978A controller
can interrupt normal net-
work behavior.
These bits are read accessible al-
ways. Write accessible when the
STOP bit is set to 1. IPG is set to
60h (96 Bit times) by H_RESET
Description
141