AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 119

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR6: RX/TX Descriptor Table Length
Bit
31-16
15-12 TLEN
11-8
Name
RES
RLEN
ble. As long as the Am79C978A
controller is not reset while in
suspend mode (by H_RESET,
S_RESET, or by setting the
STOP bit), no re-initialization of
the device is required after the
device comes out of suspend
mode. The Am79C978A control-
ler will continue at the transmit
and receive descriptor ring loca-
tions from where it had left, when
it entered the suspend mode.
This bit is always read/write ac-
cessible. SPND is cleared by
H_RESET, S_RESET, or by
setting the STOP bit.
Read accessible only when ei-
ther the STOP or the SPND bit is
set. Write operations have no ef-
fect and should not be per-
formed. TLEN is only defined
after initialization. These bits are
unaffected
S_RESET, or STOP.
Read accessible only when ei-
ther the STOP or the SPND bit is
set. Write operations have no ef-
fect and should not be per-
formed. RLEN is only defined
after initialization. These bits are
unaffected
S_RESET, or STOP.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains a copy of the transmit
encoded ring length (TLEN) field
read from the initialization block
during the Am79C978A control-
ler initialization. This field is writ-
ten
initialization routine.
Contains a copy of the receive
encoded ring length (RLEN) read
from the initialization block during
Am79C978A controller initializa-
tion. This field is written during
the
routine.
during
Am79C978A
the
by
by
Am79C978A
initialization
H_RESET,
H_RESET,
Am79C978A
7-0
CSR7: Extended Control and Interrupt 2
Certain bits in CSR7 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR7 and write back
the value just read to clear the interrupt condition.
Bit
31-16 RES
15
FASTSPNDE Fast Suspend Enable. When
RES
Name
Write operations are ignored.
zeros and read as undefined.
FASTSPNDE is set to 1, the
Am79C978A controller performs
a fast suspend whenever the
SPND bit is set.
ed, the Am79C978A controller
performs a quick entry into the
suspend mode. At the time the
SPND bit is set, the Am79C978A
controller will complete the DMA
process of any transmit and/or
receive packet that had already
begun DMA activity. In addition,
any transmit packet that had
started transmission will be fully
transmitted, and any receive
packet that had begun reception
will be fully received. However,
no additional packets will be
transmitted or received and no
additional transmit or receive
DMA activity will begin. Hence,
the Am79C978A controller may
enter the suspend mode with
transmit and/or receive packets
still in the FIFOs or the SRAM.
When FASTSPNDE is 0 and the
SPND bit is set, the Am79C978A
controller may take longer before
entering the suspend mode. At
the time the SPND bit is set, the
Am79C978A controller will com-
plete the DMA process of a trans-
mit packet if it had already begun,
and the Am79C978A controller
will completely receive a receive
packet if it had already begun.
Additionally, all transmit packets
stored in the transmit FIFOs and
the transmit buffer area in the
Reserved locations. Read as 0s.
Description
Reserved locations. Written as
When a fast suspend is request-
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