AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 32

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

dium requires an integrated 10BASE-T MAU. The
The Auto-Poll’s frequency of generating MII man-
agement frames can be adjusted by setting of the
APDW bits (BCR32, bits 10-8). The delay can be
adjusted from 0 MDC periods to 2048 MDC periods.
Auto-Poll by default will only read the MII Status
register in the external PHY.
Network Port Manager
If the external PHY is present and is active, the Net-
work Port Manager will request status from the external
PHY by generating MII management frames. These
frames will be sent roughly every 900 ms. These
frames are necessary so that the Network Port Man-
ager can monitor the current active link and can select
a different network port if the current link goes down.
10BASE-T PHY
The 10BASE-T transceiver incorporates the physical layer
function, including both clock recovery (ENDEC) and trans-
ceiver function. Data transmission over the 10BASE-T me-
transceiver will meet the electrical requirements for
10BASE-T as specified in IEEE 802.3i. The transmit signal
is filtered on the transceiver to reduce harmonic content per
IEEE 802.3i. Since filtering is performed in silicon, external
filtering modules are not needed. The 10BASE-T PHY
transceiver receives 10 Mbps data from the MAC across
the internal MII at 2.5 million nibbles per second (parallel),
or 10 million bits per second (serial) for 10BASE-T. It then
Manchester encodes the data before transmission to the
network.
The RX+ pins are differential twisted-pair receivers.
When properly terminated, each receiver will meet
the electrical requirements for 10BASE-T as speci-
fied in IEEE 802.3i. Each receiver has internal filter-
ing and does not require external filter modules. The
10BASE-T PHY transceiver receives a Manchester
coded 10BASE-T data stream from the medium. It
then recovers the clock and decodes the data. The
data stream is presented at the internal MII interface
in either parallel or serial format.
PCI and JTAG Configuration Information
The PCI device ID and software configuration information
is as follows in Table 4 and Table 5.
32
Vendor ID
00002262
1022
CSR89
Table 5. PCI Software Configuration
Table 4. PCI Device ID
Device ID
2001
00006003h
CSR88
Rev ID (offset 0x08)
2262 6003h
52
JTAG
Am79C978A
Slave Bus Interface Unit
The slave Bus Interface Unit (BIU) controls all ac-
cesses to the PCI configuration space, the Control
and Status Registers (CSR), the Bus Configuration
Registers (BCR), the Address PROM (APROM) loca-
tions, and the Expansion ROM. Table 6 shows the re-
sponse of the Am79C978A controller to each of the
PCI commands in slave mode.
Slave Configuration Transfers
The host can access the PCI configuration space with
a c on f i g u ra t i o n r e a d o r wr i t e c o m m a n d . T h e
Am79C978A controller will assert DEVSEL during the
address phase when IDSEL is asserted, AD[1:0] are
both 0, and the access is a configuration cycle. AD[7:2]
select the DWord location in the configuration space.
The Am79C978A controller ignores AD[10:8], because
C[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt
Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration
Read
Configuration
Write
Memory Read
Multiple
Dual Address
Cycle
Memory Read
Line
Memory Write
Invalidate
Table 6. Slave Commands
Command
Not used
Not used
Read of CSR, BCR, APROM,
and Reset registers
Write to CSR, BCR, and
APROM
Memory mapped I/O read of
CSR, BCR, APROM, and
Reset registers. Read of the
Expansion Bus
Memory mapped I/O write of
CSR, BCR, and APROM
Read of the Configuration
Space
Write to the Configuration
Space
Aliased to Memory Read
Not used
Aliased to Memory Read
Aliased to Memory Write
Use