AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 39

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

Master Bus Interface Unit
The master Bus Interface Unit (BIU) controls the
acquisition of the PCI bus and all accesses to the
initialization block, descriptor rings, and the re-
ceive and transmit buffer memory. Table 8 shows
the usage of PCI commands by the Am79C978A
controller in master mode.
Bus Acquisition
The microcode will determine when a DMA transfer
should be initiated. The first step in any bus master
transfer is to acquire ownership of the bus. This task is
handled by synchronous logic within the BIU. Bus own-
ership is requested with the REQ signal and ownership
is granted by the arbiter through the GNT signal.
Figure 13 shows the Am79C978A controller bus acqui-
sition. REQ is asserted and the arbiter returns GNT
while another bus master is transferring data. The
Am79C978A controller waits until the bus is idle
(FRAME and IRDY deasserted) before it starts driving
AD[31:0] and C/BE[3:0] on clock 5. FRAME is asserted
at clock 5 indicating a valid address and command on
AD[31:0] and C/BE[3:0]. The Am79C978A controller
does not use address stepping which is reflected by
ADSTEP (bit 7) in the PCI Command register being
hardwired to 0.
C[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Command
Interrupt
Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read Not used
Configuration Write Not used
Memory Read
Multiple
Dual Address Cycle Not used
Memory Read Line
Memory Write
Invalidate
Table 8. Master Commands
Use
Not used
Not used
Not used
Not used
Read of the initialization
block and descriptor
rings
Read of the transmit
buffer in non-burst mode
Write to the descriptor
rings and to the receive
buffer
Read of the transmit
buffer in burst mode
Read of the transmit
buffer in burst mode
Not used
Am79C978A
In burst mode, the deassertion of REQ depends on the
setting of EXTREQ (BCR18, bit 8). If EXTREQ is
cleared to 0, REQ is deasserted at the same time as
FRAME is asserted. (The Am79C978A controller never
performs more than one burst transaction within a sin-
gle bus mastership period.) If EXTREQ is set to 1, the
Am79C978A controller does not deassert REQ until it
starts the last data phase of the transaction.
Once asserted, REQ remains active until GNT has be-
come active and independent of subsequent setting of
STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The asser-
tion of H_RESET or S_RESET, however, will cause
REQ to go inactive immediately.
Bus Master DMA Transfers
There are four primary types of DMA transfers. The
Am79C978A controller uses non-burst as well as burst
cycles for read and write access to the main memory.
Basic Non-Burst Read Transfer
By default, the Am79C978A controller uses non-
burst cycles in all bus master read operations. All
controller non-burst read accesses are of the PCI
command type Memory Read (type 6). Note that
during a non-burst read operation, all byte lanes will
always be active. The Am79C978A controller will
internally discard unneeded bytes.
The Am79C978A controller typically performs more
than one non-burst read transaction within a single bus
mastership period. FRAME is dropped between con-
secutive non-burst read cycles. REQ stays asserted
until FRAME is asserted for the last transaction. The
FRAME
C/BE
IRDY
REQ
GNT
CLK
AD
Figure 13. Bus Acquisition
1
2
3
4
ADDR
CMD
22399A-16
5
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