AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 127

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR26: Next Receive Descriptor Address Lower
Bit
31-16
15-0
CSR27: Next Receive Descriptor Address Upper
Bit
31-16
15-0
CSR28: Current Receive Descriptor Address Lower
Bit
31-16
15-0
Name
RES
NRDAL
Name
RES
NRDAU
Name
RES
CRDAL
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
next receive descriptor address
pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
next receive descriptor address
pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of
the current receive descriptor
address pointer.
Am79C978A
CSR29: Current Receive Descriptor Address Upper
Bit
31-16 RES
15-0
CSR30: Base Address of Transmit Ring Lower
Bit
31-16 RES
15-0
CSR31: Base Address of Transmit Ring Upper
Bit
31-16 RES
15-0
CSR32: Next Transmit Descriptor Address Lower
Bit
31-16 RES
15-0
Name
CRDAU
Name
BADXL
Name
BADXU
Name
NXDAL
zeros and read as undefined.
the current receive descriptor
address pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
base address of the Transmit
Ring.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
base address of the Transmit
Ring.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
the next transmit descriptor
address pointer.
Description
Reserved locations. Written as
Contains the upper 16 bits of
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of
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