AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 126

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR19: Current Receive Buffer Address Upper
Bit
31-16
15-0
CSR20: Current Transmit Buffer Address Lower
Bit
31-16
15-0
CSR21: Current Transmit Buffer Address Upper
Bit
31-16
15-0
CSR22: Next Receive Buffer Address Lower
Bit
31-16
126
Name
RES
CRBAU
Name
RES
CXBAL
Name
RES
CXBAU
Name
RES
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
current receive buffer address at
which the Am79C978A controller
will store incoming frame data.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
current transmit buffer address
from which the Am79C978A con-
troller is transmitting.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
current transmit buffer address
from which the Am79C978A con-
troller is transmitting.
Description
Reserved locations. Written as
zeros and read as undefined.
Am79C978A
15-0
CSR23: Next Receive Buffer Address Upper
Bit
31-16 RES
15-0
CSR24: Base Address of Receive Ring Lower
Bit
31-16 RES
15-0
CSR25: Base Address of Receive Ring Upper
Bit
31-16 RES
15-0
Name
NRBAU
Name
BADRL
Name
BADRU
NRBAL
next receive buffer address to
which the Am79C978A controller
will store incoming frame data.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
next receive buffer address to
which the Am79C978A controller
will store incoming frame data.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
base address of the Receive
Ring.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
base address of the Receive
Ring.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the