AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 198

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

RMD0
Bit
31-0
RMD1
Bit
31
30
29
28
198
RBADR
OWN
ERR
FRAM
OFLO
Name
Name
Receive Buffer address. This field
contains the address of the
receive buffer that is associated
with this descriptor.
This bit indicates whether the de-
scriptor entry is owned by the
host (OWN = 0) or by the
Am79C978A controller (OWN =
1). The Am79C978A controller
clears the OWN bit after filling
the buffer that the descriptor
points to. The host sets the OWN
bit after emptying the buffer.
Once the Am79C978A controller
or host has relinquished owner-
ship of a buffer, it must not
change any field in the descriptor
entry.
ERR is the OR of FRAM, OFLO,
CRC, BUFF, or BPE. ERR is set
by the Am79C978A controller
and cleared by the host.
Framing error indicates that the
incoming frame contains a non-
integer multiple of eight bits and
there was an FCS error. If there
was no FCS error on the incom-
ing frame, then FRAM will not be
set even if there was a non-
integer multiple of eight bits in the
frame. FRAM is not valid in inter-
nal loopback mode. FRAM is val-
id only when ENP is set and
OFLO is not. FRAM is set by the
Am79C978A
cleared by the host.
Overflow error indicates that the
receiver has lost all or part of the
incoming frame, due to an inability
to move data from the receive
FIFO into a memory buffer before
the internal FIFO overflowed.
OFLO is set by the Am79C978A
controller and cleared by the host.
Description
Description
controller
Am79C978A
and
27
26
25
24
CRC
BUFF
STP
ENP
CRC indicates that the receiver
Buffer error is set any time the
has detected a CRC (FCS) error
on the incoming frame. CRC is
valid only when ENP is set and
OFLO is not. CRC is set by the
Am79C978A
cleared by the host. CRC will also
be set when Am79C978A home
networking receives an RX_ER
indication from the external PHY
through the MII.
Am79C978A controller does not
own the next buffer while data
chaining a received frame. This
can occur in either of two ways:
1. The OWN bit of the next buffer
2. FIFO overflow occurred before
If a Buffer Error occurs, an Over-
flow Error may also occur inter-
nally in the FIFO, but will not be
reported in the descriptor status
entry unless both BUFF and
OFLO errors occur at the same
time.
Am79C978A
cleared by the host.
Start of Packet indicates that this
is the first buffer used by the
Am79C978A controller for this
frame. If STP and ENP are both
set to 1, the frame fits into a sin-
gle buffer. Otherwise, the frame
is spread over more than one
buffer. When LAPPEN (CSR3,
bit 5) is cleared to 0, STP is set
by the Am79C978A controller
and cleared by the host. When
LAPPEN is set to 1, STP must be
set by the host.
End of Packet indicates that this is
the last buffer used by the
Am79C978A controller for this
frame. It is used for data chaining
buffers. If both STP and ENP are
set, the frame fits into one buffer
and there is no data chaining.
ENP is set by the Am79C978A
controller and cleared by the host.
is 0.
the Am79C978A controller
was able to read the OWN bit
of the next descriptor.
BUFF
is
controller
controller
set
by
and
and
the