AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 156

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

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DWIO
BR E A DE
This bit is read accessible al-
ways, write accessible only when
either the STOP or the SPND bit
is set. EXTREQ is cleared by
H_RESET and is not affected by
S_RESET or STOP.
Double Word I/O. When set, this
bit indicates that the Am79C978A
controller is programmed for
DWord I/O (DWIO) mode. When
cleared, this bit indicates that the
Am79C978A controller is pro-
grammed for Word I/O (WIO)
mode. This bit affects the I/O Re-
source Offset map and it affects
the
Am79C978A controller’s I/O re-
sources. See the DWIO and WIO
sections for more details.
The initial value of the DWIO bit is
determined by the programming
of the EEPROM.
The value of DWIO can be al-
tered
Am79C978A controller. Specifi-
cally, the Am79C978A controller
will set DWIO if it detects a
DWord write access to offset 10h
from the Am79C978A controller’s
I/O base address (corresponding
to the RDP resource).
Once the DWIO bit has been set
to a 1, only a H_RESET or an EE-
PROM read can reset it to a 0.
(Note that the EEPROM read op-
eration will only set DWIO to a 0 if
the appropriate bit inside of the
EEPROM is set to 0.)
This bit is read accessible al-
ways. DWIO is read only, write
operations have no effect. DWIO
is cleared by H_RESET and is
not affected S_RESET or by set-
ting the STOP bit.
B ur s t R ea d E na b l e. W h en
s et , t hi s bi t e n ab l es b ur s t
m od e d ur in g m e mo r y r e ad
ac c e s s e s .
th i s b i t p r e v en t s th e d ev i c e
fr o m
du r i n g r e ad a c c e s s es . T he
defined
p er f o r mi n g
automatically
W h en
width
c l ea r e d,
b ur s t i ng
by
of
Am79C978A
the
the
5
4-3
PHYSEL[1:0] PHYSEL[1:0] bits allow for soft-
BWRITE
Burst Write Enable. When set,
A m7 9 C9 7 8A c o n tr o l l er c an
p er f or m
wh e n r e ad i ng th e i n i ti a li z a -
ti o n bl o c k , t he d es c r i p to r
r i ng
S W S T Y LE = 3 ) ,
b uf fe r m e mo r y .
BREADE should be set to 1
when the Am79C978A control-
ler is used in a PCI bus applica-
tion to guarantee maximum
performance.
This bit is read accessible al-
ways; write accessible only when
either the STOP or the SPND bit
is set. BREADE is cleared by
H_RESET and is not affected by
S_RESET or STOP.
this bit enables burst mode during
memory write accesses. When
cleared, this bit prevents the de-
vice from performing bursting
during
Am79C978A controller can per-
form burst transfers when writing
the descriptor ring entries (when
SWSTYLE = 3), and the buffer
memory.
BWRITE should be set to 1
when the Am79C978A control-
ler is used in a PCI bus applica-
tion to guarantee maximum
performance.
This bit is read accessible al-
ways, write accessible only when
either the STOP or the SPND bit
is set. BWRITE is cleared by
H_RESET and is not affected by
S_RESET or STOP.
ware controlled selection of differ-
ent operation and test modes. The
normal mode of operation is when
both bits 0 and 1 are set to 0 to se-
lect the Expansion ROM/Flash.
Setting bit 0 to 1 and bit 1 to 0 al-
lows snooping of the internal MII-
compatible bus to allow External
Address
(EADI). See Table 38 for details.
write
e nt r i es
Detection
b ur s t
accesses.
a n d
tr a n s fe r s
Interface
( wh en
The
t he