AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 251

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

HomePNA Analog Ground 28
HomePNA Analog Power 28
HomePNA Digital Power 28
HomePNA PHY Framing 75
HomePNA PHY Network Interface 27
HomePNA Physical Layer (PHY) 1
HPR0
HPR1
HPR2 and HPR3
HPR4-HPR7
HPR16
HPR18 and HPR19
HPR20 and HPR21
HPR22
HPR23
HPR24
HPR25
HPR26
HPR27
HPR28
HPR29
HRTXRXP/HRTXRXN 27
I
I/O Buffer Ground (17 Pins) 27
I/O Buffer Power (7 Pins) 27
I/O Map In DWord I/O Mode (DWIO = 1) 97
I/O Map in DWord I/O Mode (DWIO = 1) 97
I/O Map In Word I/O Mode (DWIO = 0) 96
I/O Registers 95
I/O Resources 95
IDSEL 21
IEEE 1149.1 (1990) Test Access Port Interface 26, 90
IEEE 1149.1 Supported Instruction Summary 90
IEEE 802.3 Frame And Length Field Transmission Or-
IEEE 802.3u 2
Initialization 56
Initialization Block 195
HomePNA PHY MII Control (Register 0) 187
HomePNA PHY MII Status (Register 1) 188
HomePNA PHY MII PHY ID (Registers 2 and 3)
HomePNA PHY Auto-Negotiation (Registers 4 - 7)
HomePNA PHY Control (Register 16) 190
HomePNA PHY TxCOMM (Registers 18 and 19)
HomePNA PHY RxCOMM (Registers 20 and 21)
HomePNA PHY AID (Register 22) 192
HomePNA PHY Noise Control (Register 23) 192
HomePNA PHY Noise Control 2 (Register 24) 192
HomePNA PHY Noise Statistics (Register 25) 193
HomePNA PHY Event Status (Register 26) 193
HomePNA PHY Event Status (Register 27) 194
HomePNA PHY ISBI Control (Register 28) 194
HomePNA PHY TX Control (Register 29) 194
der 70
189
189
191
191
Am79C978A
Initialization Block (SSIZE32 = 0) 195
Initialization Block (SSIZE32 = 1) 195
Initialization Block DMA Transfers 49
Initialization Block Read In Burst Mode 50
Initialization Block Read In Non-Burst Mode 50
Initialization Device Select 21
Initiator Ready 22
Input Setup and Hold Timing 226
Instruction Register and Decoding Logic 90
INTA 22
Integrated Controllers 10
Integrated PCI Ethernet controller 2
Integrated Repeater/Hub Devices 10
Inter Packet Gap (IPG) 2
Interrupt Request 22
Introduction B-1
IRDY 22
IREF 26
J
Jabber Function 72
JAM Signal 77
JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling
JTAG (IEEE 1149.1) Test Signal Timing 220, 229
K
Key to Switching Waveforms 225
L
LADRF 196
LAPP 3 Buffer Grouping B-5
LAPP 3 Buffer Grouping for Two-interrupt Method B-10
LAPP Software Requirements B-5
LAPP Timeline B-4
LAPP Timeline for Two-Interrupt Method B-9
Late Collision 67
LED Control Logic 86
LED Default Configuration 86
LED Support 84
LED0 24
LED1 24
LED2 24
LED3 24
LED4 24
Legal I/O Accesses in Double Word I/O Mode (DWIO
Legal I/O Accesses in Word I/O Mode (DWIO = 0) 96
Link Change Detect 87
Listed by Group 15
Look-Ahead Packet Processing (LAPP) 2
Look-Ahead Packet Processing (LAPP) Concept B-1
Loopback Configuration 125
Loopback Operation 70
Loss of Carrier 67
Low Latency Receive Configuration 81
228
=1) 97
Index-5