AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 89

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

When the controller detects a Magic Packet frame, it sets
the MPMAT bit (CSR116, bit 5), the MPINT bit (CSR5, bit
4), and the PME_STATUS bit (PMCSR, bit 15). If the
PME_EN or the PME_EN_OVR bits are set, the PME will
be asserted as well. If IENA (CSR0, bit 6) and MPINTE
(CSR5, bit 3) are set to 1, INTA will be asserted. Any one
of the four LED pins can be programmed to indicate that
a Magic Packet frame has been received. MPSE (BCR4-
7, bit 9) must be set to 1 to enable that function.
CAUTION: The polarity of the LED pin can be pro-
grammed to be active HIGH by setting LEDPOL
(BCR4-7, bit 14) to 1.
Once a Magic Packet frame is detected, the con-
troller will discard the frame internally, but will not
resume normal transmit and receive operations
BCR Bit Number 15
Pattern Match
RAM Address
J+m
2+n
63
0
1
2
J
39
Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0 Pattern Control End Pattern P
Data Byte 4n+3
Data Byte 3
Data Byte 3
P3 pointer
P7 pointer
PMR_B4
32 31
BCR 47
8
7
Date Byte 4n+2
Data Byte 2
Data Byte 2
P2 pointer
P6 pointer
PMR_B3
Figure 48. Pattern Match RAM
Pattern Match RAM Bit Number
24
0 15
Am79C978A
Data Byte 4n+1
23
Data Byte 1
Data Byte1
P1 pointer
P5 pointer
PMR_B2
until PG is asser ted or MPEN is cleared. Once
both of these events has occurred, indicating that
the system has detected the Magic Packet and is
awake, the controller will continue polling receive
and transmit descriptor rings where it left off. It is
not necessary to re-initialize the device. If the part
is re-initialized, then the descriptor locations will
be reset and the controller will not start where it
left off.
If magic packet mode is disabled by the assertion of PG,
then in order to immediately re-enable Magic Packet
mode, the PG pin must remain deasserted for at least 200
ns before it is reasserted. If Magic Packet mode is dis-
abled by clearing MPEN bit, then it may be immediately
re-enabled by setting MPEN back to 1.
BCR 46
8
16
Data Byte 4n+0
7
15
Data Byte 0
Data Byte 0
P0 pointer
P4 pointer
PMR_B1
7
EOP
6
8
0 15
5
SKIP
7
Pattern Control
Pattern Control End Pattern P
Pattern Control
Pattern Enable
PMR_B0
BCR 45
4
bits
X
3
2
0
8
MASK
1
First Address
Last Address
Start Pattern
Start Pattern
Comments
Address
Second
0
22399A-51
P
P
1
k
89
1
k