AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 167

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

BCR31: Software Timer Register
Bit
31-16 RES
15-0
BCR32: PHY Control and Status Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15
STVAL
ANTST
Name
Name
Reserved locations. Written as
zeros and read as undefined.
Software Timer Value. STVAL
controls the maximum time for
the Software Timer to count be-
fore
(CSR7, bit 11) interrupt. The
Software Timer is a free-running
timer that is started upon the first
write to STVAL. After the first
write, the Software Timer will
continually count and set the
STINT interrupt at the STVAL
period.
The STVAL value is interpreted
as an unsigned number with a
resolution of 256 Time Base
Clock periods. For instance, a
value of 122 ms would be pro-
grammed with a value of 9531
(253Bh) if the Time Base Clock is
running at 20 MHz. A value of 0 is
undefined and will result in erratic
behavior.
Read and write accessible al-
ways. STVAL is set to FFFFh af-
ter H_RESET and is unaffected
by S_RESET and the STOP bit.
Reserved locations. Written as
zeros and read as undefined.
Reserved
tests. Written as 0 and read as
undefined.
Note: Use of this bit will cause
data corruption and erroneous
operation.
This bit is always read/write ac-
cessible. ANTST is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
Description
Description
generating
for
manufacturing
the
STINT
Am79C978A
14
13-12 FMDC
MIIPD
MII PHY Detect (is used for man-
Fast Management Data Clock (is
ufacturing tests). MIIPD reflects
the quiescent state of the MDIO
pin. MIIPD is continuously updat-
ed whenever there is no manage-
ment operation in progress on the
MII interface. When a manage-
ment operation begins on the in-
terface, the state of MIIPD is
preserved until the operation
ends, when the quiescent state is
again monitored and continuous-
ly updates the MIIPD bit. When
the MDIO pin is at a quiescent
LOW state, MIIPD is cleared to 0.
When the MDIO pin is at a quies-
cent HIGH state, MIIPD is set to
1. MIIPD is used by the automatic
port selection logic to select the
MII port. When the Auto Select bit
(ASEL, BCR2, bit 1) is a 1 and the
MIIPD bit is a 1, the MII port is se-
lected. Any transition on the MI-
IPD bit will set the MIIPDTI bit in
CSR7, bit 3.
Read accessible always. MIIPD
is read only. Write operations
are ignored and should not be
performed.
used for manufacturing tests).
When FMDC is set to 2h the MII
Management Data Clock will run
at 10 MHz max. The Manage-
ment Data Clock will no longer be
IEEE 802.3u-compliant and set-
ting this bit should be used with
care. The accompanying external
PHY must also be able to accept
management frames at the new
clock rate. When FMDC is set to
1h, the MII Management Data
Clock will run at 5 MHz max. The
Management Data Clock will no
longer be IEEE 802.3u-compliant
and setting this bit should be
used with care. The accompany-
ing external PHY must also be
able
frames at the new clock rate.
When FMDC is set to 0h, the MII
Management Data Clock will run
at 2.5 MHz max and will be fully
to
accept
management
167