AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 128

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR33: Next Transmit Descriptor Address Upper
Bit
31-16
15-0
CSR34: Current Transmit Descriptor Address
Lower
Bit
31-16
15-0
CSR35: Current Transmit Descriptor Address
Upper
Bit
31-16
15-0
128
Name
RES
NXDAU
Name
RES
CXDAL
Name
RES
CXDAU
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
next transmit descriptor address
pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of
the current transmit descriptor
address pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of
the current transmit descriptor
address pointer.
Am79C978A
CSR36: Next Next Receive Descriptor Address
Lower
Bit
31-16 RES
15-0
CSR37: Next Next Receive Descriptor Address
Upper
Bit
31-16 RES
15-0
CSR38: Next Next Transmit Descriptor Address
Lower
Bit
31-16 RES
15-0
Name
NNRDAL
Name
NNRDAU
Name
NNXDAL
zeros and read as undefined.
the next next receive descriptor
address pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
the next next receive descriptor
address pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
next next transmit descriptor
address pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
Reserved locations. Written as
Contains the lower 16 bits of
Description
Reserved locations. Written as
Contains the upper 16 bits of
Description
Reserved locations. Written as
Contains the lower 16 bits of the