AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 116

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

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MFCO
MFCOM
UINTCMD
UINT
RCVCCO
by H_RESET or S_RESET and is
unaffected by the STOP bit.
When MFCO is set, INTA is as-
serted if IENA is 1 and the mask
bit MFCOM is 0.
This bit is always read/write ac-
cessible. MFCO is cleared by the
host by writing a 1. Writing a 0
has no effect. MFCO is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
This bit is always read/write ac-
cessible. MFCOM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
This bit is always read/write ac-
cessible. UINTCMD is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
This bit is always read/write ac-
cessible. UINT is cleared by the
host by writing a 1. Writing a 0
has no effect. UINT is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
Missed Frame Counter Overflow is
set by the Am79C978A controller
when the Missed Frame Counter
(CSR112
wrapped around.
Missed Frame Counter Overflow
Mask. If MFCOM is set, the MFCO
bit will be masked and unable to
set the INTR bit.
User
UINTCMD can be used by the
host to generate an interrupt un-
related to any network activity.
When UINTCMD is set, INTA is
asserted if IENA is set to 1. Write
a 1 to UINT to clear UINTCMD
and stop interrupts.
User Interrupt. UINT is set by the
Am79C978A controller after the
host has issued a user interrupt
command by setting UINTCMD
(CSR4, bit 7) to 1.
Receive Collision Counter Over-
flow is set by the Am79C978A
Interrupt
and
CSR113)
Command.
Am79C978A
has
4
3
2
1-0
CSR5: Extended Control and Interrupt 1
Certain bits in CSR5 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
RCVCCOM Receive Collision Counter Over-
TXSTRT
TXSTRTM Transmit
RES
controller when the Receive Col-
lision Counter (CSR114 and
CSR115) has wrapped around.
When RCVCCO is set, INTA is
asserted if IENA is 1 and the
mask bit RCVCCOM is 0.
This bit is always read/write ac-
cessible. RCVCCO is cleared by
the host by writing a 1. Writing a
0 has no effect. RCVCCO is
cleared
S_RESET, or by setting the
STOP bit.
flow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
This bit is always read/write ac-
cessible. RCVCCOM is set to 1
by H_RESET or S_RESET and is
not affected by the STOP bit.
Am79C978A controller whenever
it begins transmission of a frame.
When TXSTRT is set, INTA is as-
serted if IENA is 1 and the mask
bit TXSTRTM is 0.
This bit is always read/write ac-
cessible. TXSTRT is cleared by
the host by writing a 1. Writing a 0
has no effect. TXSTRT is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
TXSTRTM is set, the TXSTRT
bit will be masked and unable
to set the INTR bit.
This bit is always read/write ac-
cessible. TXSTRTM is set to 1
by H_RESET or S_RESET and
is not affected by the STOP bit.
zeros and read as undefined.
Transmit Start status is set by the
Reserved locations. Written as
Start
by
Mask.
H_RESET,
If