AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 161

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

SWSTYLE
All Other
[7:0]
00h
01h
02h
03h
not affected by S_RESET or
STOP.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32-bit address
bus during master accesses initi-
ated by the Am79C978A control-
ler. This action is required, since
the 16-bit software structures
specified by the SSIZE32 = 0 set-
ting will yield only 24 bits of ad-
dress for Am79C978A controller
bus master accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to the Am79C978A controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the Am79C978A
controller for performing master
accesses.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
PCnet-PCI
PCnet-PCI
PCnet-ISA
controller
controller
controller
LANCE/
Name
Style
RES
RES
Table 41. Software Styles
Am79C978A
Undefined
SSIZE32
0
1
1
1
7-0
16-bit software
structures, non-burst or
burst access
RES
32-bit software
structures, non-burst or
burst access
32-bit software
structures, non-burst or
burst access
Undefined
SWSTYLE
Initialization Block
Entries
Note that the setting of the
SSIZE32 bit has no effect on the
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit
(BCR18, bit 7).
Software Style register. The val-
ue in this register determines the
style of register and memory re-
sources that shall be used by the
Am79C978A controller. The Soft-
ware Style selection will affect the
interpretation of a few bits within
the CSR space, the order of the
descriptor entries and the width of
the descriptors and initialization
block entries.
All Am79C978A CSR bits and all
descriptor, buffer, and initialization
block entries not cited in Table 41
are unaffected by the Software
Style selection and are, therefore,
always fully functional as specified
in the CSR and BCR sections.
Read/Write accessible only when
either the STOP or the SPND bit
is set. The SWSTYLE register will
contain the value 00h following
H_RESET and will be unaffected
by S_RESET or STOP.
16-bit software structures,
non-burst access only
RES
32-bit software structures,
non-burst access only
32-bit software structures,
non-burst or burst access
Undefined
Descriptor Ring Entries
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