AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 134

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR64: Next Transmit Buffer Address Lower
Bit
31-16 RES
15-0
CSR65: Next Transmit Buffer Address Upper
Bit
31-16 RES
15-0
CSR66: Next Transmit Byte Count
Bit
31-16 RES
15-12 RES
11-0
134
NXBAL
NXBAU
Name
NXBC
Name
Name
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
next transmit buffer address from
which the Am79C978A controller
will transmit an outgoing frame.
These bits are read/write accessi-
ble only when either the STOP or
the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
next transmit buffer address from
which the Am79C978A controller
will transmit an outgoing frame.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Read and
written as zeros.
Next Transmit Byte Count. This field
is a copy of the BCNT field of TMD1
of the next transmit descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
Description
Am79C978A
CSR67: Next Transmit Status
Bit
31-16 RES
15-0
7-0
CSR72: Receive Ring Counter
Bit
31-16 RES
15-0
CSR74: Transmit Ring Counter
Bit
31-16 RES
15-0
NXST
RES
RCVRC
XMTRC
Name
Name
Name
Reserved locations. Written as
Reserved locations. Written as
Receive Ring Counter location.
Reserved locations. Written as
zeros and read as undefined.
Next Transmit Status. This field is
a copy of bits 31-16 of TMD1 of
the next transmit descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Read and
written as zeros. Accessible only
when either the STOP or the
SPND bit is set.
zeros and read as undefined.
Contains a two’s complement bi-
nary number used to number the
current receive descriptor. This
counter interprets the value in
CSR76 as pointing to the first de-
scriptor. A counter value of zero
corresponds to the last descriptor
in the ring.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
Transmit Ring Counter location.
Contains a two’s complement bi-
nary number used to number the
current transmit descriptor. This
counter interprets the value in
CSR78 as pointing to the first de-
scriptor. A counter value of zero
corresponds to the last descriptor
in the ring.
Description
Description
Description