AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 124

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR15: Mode
This register’s fields are loaded during the Am79C978A
controller initialization routine with the corresponding
Initialization Block values, or when a direct register write
has been performed on this register.
Bit
31-16
15
14
13
12-9
8-7 PORTSEL[1:0] Port Select bits allow for soft-
124
Name
RES
PROM
DRCVBC
DRCVPA
RES
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
Description
Reserved locations. Written as
zeros and read as undefined.
Promiscuous
PROM = 1, all incoming receive
frames are accepted.
Disable
When
Am79C978A controller from re-
ceiving
Used for protocols that do not
support broadcast addressing,
except as a function of multicast.
DRCVBC is cleared by activation
of
(broadcast messages will be re-
ceived) and is unaffected by
STOP.
Disable Receive Physical Ad-
dress. When set, the physical
address detection (Station or
node ID) of the Am79C978A
controller
Frames addressed to the nodes
individual physical address will
not be recognized.
Reserved locations. Written as
zeros and read as undefined.
ware controlled selection of the
H_RESET
broadcast
set,
Receive
will
Mode.
disables
or
be
messages.
Broadcast.
S_RESET
disabled.
When
Am79C978A
the
6
5
4
3
This bit is read/write accessible only when ei-
INTL
DRTY
FCOLL
DXMTFCS Disable Transmit CRC (FCS).
network medium. The only legal
values for this field is 11.
ther the STOP or the SPND bit is
set. Cleared by H_RESET or
S_RESET and is unaffected by
STOP.
scription of LOOP (CSR15, bit 2).
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
to 1, the Am79C978A controller
will attempt only one transmission.
In this mode, the device will not
protect the first 64 bytes of frame
data in the Transmit FIFO from
being overwritten, because auto-
matic retransmission will not be
necessary. When DRTY is set to
0, the Am79C978A controller will
attempt 16 transmissions before
signaling a retry error.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
the collision logic to be tested.
The Am79C978A controller must
be in internal loopback for FCOLL
to be valid. If FCOLL = 1, a colli-
sion will be forced during loop-
back
which will result in a Retry Error.
If FCOLL = 0, the Force Collision
logic will be disabled. FCOLL is
defined after the initialization
block is read.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
When DXMTFCS is set to 0, the
transmitter will generate and ap-
pend an FCS to the transmitted
frame. When DXMTFCS is set to
1, no FCS is generated or sent
with
DXMTFCS is overridden when
ADD_FCS and ENP bits are set
in TMD1.
Internal Loopback. See the de-
Disable Retry. When DRTY is set
Force Collision. This bit allows
the
transmission
transmitted
attempts,
frame.