AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 98

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

USER ACCESSIBLE REGISTERS
The Am79C978A controller has four types of user reg-
isters: the PCI configuration registers, the Control and
Status registers (CSRs), the Bus Control registers
(BCRs), 10BASE-T PHY Management registers
(TBRs), and 1 Mbps HomePNA PHY Management
registers (HPRs).
The Am79C978A controller implements all PCnet-ISA
(Am79C960) registers, all C-LANCE (Am79C90) regis-
ters, plus a number of additional registers. The
Am79C978A CSRs are compatible upon power up with
both the PCnet-ISA CSRs and all of the C-LANCE
CSRs.
The PCI configuration registers can be accessed in any
data width. All other registers must be accessed accord-
ing to the I/O mode that is currently selected. When WIO
mode is selected, all other register locations are defined
to be 16 bits in width. When DWIO mode is selected, all
these register locations are defined to be 32 bits in
width, with the upper 16 bits of most register locations
marked as reserved locations with undefined values.
When performing register write operations in DWIO
mode, the upper 16 bits should always be written as
zeros. When performing register read operations in
DWIO mode, the upper 16 bits of I/O resources should
always be regarded as having undefined values, except
for CSR88.
The Am79C978A registers can be divided into four
groups: PCI Configuration, Setup, Running, and Test.
Registers not included in any of these categories can
be assumed to be intended for diagnostic purposes.
n PCI Configuration Registers
These registers are intended to be initialized by the sys-
tem initialization procedure (e.g., BIOS device initializa-
tion routine) to program the operation of the controller
PCI bus interface.
The following is a list of the registers that would typically
need to be programmed once during the initialization of
the Am79C978A controller within a system:
n Setup Registers
These registers are intended to be initialized by the de-
vice driver to program the operation of various controller
features.
98
— PCI I/O Base Address or Memory Mapped I/O
— PCI Expansion ROM Base Address register
— PCI Interrupt Line register
— PCI Latency Timer register
— PCI Status register
— PCI Command register
— OnNow register
Base Address register
Am79C978A
The following is a list of the registers that would typically
need to be programmed once during the setup of the
controller within a system. The control bits in each of
these registers typically do not need to be modified once
they have been written. However, there are no restric-
tions as to how many times these registers may actually
be accessed. Note that if the default power up values
of any of these registers is acceptable to the application,
then such registers need never be accessed at all.
Note: Registers marked with “^” may be programma-
ble through the EEPROM read operation and, there-
fore, do not necessarily need to be written to by the
system initialization procedure or by the driver soft-
ware. Registers marked with “*” will be initialized by the
initialization block read operation.
CSR1
CSR2*
CSR3
CSR4
CSR5
CSR7
CSR8*
CSR9*
CSR10*
CSR11*
CSR12*^
CSR13*^
CSR14*^
CSR15*
CSR24*
CSR25*
CSR30*
CSR31*
CSR47*
CSR49*
CSR76*
CSR78*
CSR80
CSR82
CSR100
CSR116^
CSR122
Control
Initialization Block Address[15:0]
Initialization Block Address[31:16]
Interrupt Masks and Deferral Control
Test and Features Control
Extended Control and Interrupt
Extended Control and Interrupt2
Logical Address Filter[15:0]
Logical Address Filter[31:16]
Logical Address Filter[47:32]
Logical Address Filter[63:48]
Physical Address[15:0]
Physical Address[31:16]
Physical Address[47:32]
Mode
Base Address of Receive Ring Lower
Base Address of Receive Ring Upper
Base Address of Transmit Ring Lower
Base Address of Transmit Ring Upper
Transmit Polling Interval
Receive Polling Interval
Receive Ring Length
Transmit Ring Length
DMA Transfer Counter and FIFO Threshold
Bus Activity Timer
Memory Error Timeout
OnNow Miscellaneous
Receiver Packet Alignment Control