IPR-NIOS Altera, IPR-NIOS Datasheet - Page 104

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–58
Table 3–44. Unconditional Jump and Call Instructions
Table 3–45. Conditional Branch Instructions
Nios II Processor Reference Handbook
call
callr
ret
jmp
jmpi
br
bge
bgeu
bgt
bgtu
ble
bleu
blt
bltu
beq
bne
Instruction
Instruction
Program Control Instructions
This instruction calls a subroutine using an immediate value as the subroutine's absolute address, and
stores the return address in register ra.
This instruction calls a subroutine at the absolute address contained in a register, and stores the return
address in register ra. This instruction serves the roll of dereferencing a C function pointer.
The ret instruction is used to return from subroutines called by call or callr. ret loads and executes the
instruction specified by the address in register ra.
The jmp instruction jumps to an absolute address contained in a register. jmp is used to implement switch
statements of the C programming language.
The jmpi instruction jumps to an absolute address using an immediate value to determine the absolute
address.
This instruction branches relative to the current instruction. A signed immediate value gives the offset of the
next instruction to execute.
The Nios II architecture supports the unconditional jump, branch, and call
instructions listed in
The conditional branch instructions compare register values directly, and branch if the
expression is true. Refer to
equality and relational comparisons of the C programming language:
■
■
■
The conditional branch instructions do not have delay slots.
== and !=
< and <= (signed and unsigned)
> and >= (signed and unsigned)
These instructions provide relative branches that compare two register values and branch if the
expression is true. Refer to
relational operations implemented.
Table
Table
3–44. These instructions do not have delay slots.
“Comparison Instructions” on page 3–57
3–45. The conditional branches support the following
Description
Description
December 2010 Altera Corporation
Chapter 3: Programming Model
for a description of the
Instruction Set Categories