IPR-NIOS Altera, IPR-NIOS Datasheet - Page 69

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Registers
Table 3–25. mpuacc Control Register Fields for MASK Variation
Table 3–26. mpuacc Control Register Fields for LIMIT Variation
Table 3–27. mpuacc Control Register Field Descriptions (Part 1 of 2)
December 2010 Altera Corporation
31
Note to
(1) This field size is variable. Unused upper bits and unused lower bits must be written as zero.
31
Note to
(1) This field size is variable. Unused upper bits and unused lower bits must be written as zero.
MASK
LIMIT
C
PERM
0
30
30
Field
(1)
Table
Table
(1)
29
29
28
28
3–25:
3–26:
MASK specifies the size of the region.
LIMIT specifies the upper address limit of the region.
C is the data cacheable flag. C only applies to MPU data regions and
determines the default cacheability of a data region. When C = 0, the
data region is uncacheable. When C = 1, the data region is
cacheable.
PERM specifies the access permissions for the region.
27
27
26
26
The INDEX and D fields specify the region information to access when an MPU region
read or write operation is performed. The D field specifies whether the region is a data
region or an instruction region. The INDEX field specifies which of the 32 data or
instruction regions to access. If there are fewer than 32 instruction or 32 data regions,
unused high-order bits must be written as zero and are read as zero.
Refer to
information on MPU region read and write operations.
The mpuacc Register
The mpuacc register works in conjunction with the mpubase register to set and retrieve
MPU region information and is only available in systems with an MPU. The mpuacc
register consists of attributes that will be set or have been retrieved which define the
MPU region. The mpuacc register only holds a portion of the attributes that define an
MPU region. The remaining portion of the MPU region definition is held by the BASE
field of the mpubase register.
An SOPC Builder generation-time option controls whether the mpuacc register
contains a MASK or LIMIT field.
the MASK field.
Table 3–27
25
25
24
24
23
23
“MPU Region Read and Write Operations” on page 3–29
22
22
gives details of the fields defined in the mpuacc register.
21
21
Table 3–26
20
20
Description
LIMIT
19
MASK
19
18
18
(1)
shows the layout of the mpuacc register with the LIMIT field.
(1)
17
17
16
16
Table 3–25
15
15
14
14
13
13
shows the layout of the mpuacc register with
12
12
11
11
10
10
Read/Write
Read/Write
Read/Write
Read/Write
9
9
Access
8
8
Nios II Processor Reference Handbook
7
7
6
6
Reset
for more
C
C
5
5
0
0
0
0
4
4
PERM
PERM
3
3
Available
Only with
Only with
Only with
Only with
MPU
MPU
MPU
MPU
2
2
1
1
3–23
0
0