IPR-NIOS Altera, IPR-NIOS Datasheet - Page 105

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Instruction Set Categories
Table 3–46. Other Control Instructions
December 2010 Altera Corporation
trap
eret
break
bret
rdctl
wrctl
flushd
flushda
flushi
initd
initda
initi
flushp
sync
rdprs
wrprs
Instruction
Other Control Instructions
Custom Instructions
No-operation Instruction
f
The trap and eret instructions generate and return from exceptions. These instructions are similar to the
call/ret pair, but are used for exceptions. trap saves the status register in the estatus register, saves
the return address in the ea register, and then transfers execution to the general exception handler. eret
returns from exception processing by restoring status from estatus, and executing the instruction
specified by the address in ea.
The break and bret instructions generate and return from breaks. break and bret are used exclusively
by software debugging tools. Programmers never use these instructions in application code.
These instructions read and write control registers, such as the status register. The value is read from or
stored to a general-purpose register.
These instructions are used to manage the data and instruction cache memories.
This instruction flushes all prefetched instructions from the pipeline. This is necessary before jumping to
recently-modified instruction memory.
This instruction ensures that all previously-issued operations have completed before allowing execution of
subsequent load and store operations.
These instructions read and write a general-purpose registers between the current register set and another
register set.
wrprs can set r0 to 0 in a shadow register set. System software must use wrprs to initialize r0 to 0 in
each shadow register set before using that register set.
Table 3–46
The custom instruction provides low-level access to custom instruction logic. The
inclusion of custom instructions is specified in SOPC Builder at system generation
time, and the function implemented by custom instruction logic is design dependent.
For further details, refer to the “Custom Instructions” section of the
Architecture
Instruction User
Machine-generated C functions and assembly language macros provide access to
custom instructions, and hide implementation details from the user. Therefore, most
software developers never use the custom assembly language instruction directly.
The Nios II assembler provides a no-operation instruction, nop.
shows other control instructions.
chapter of the Nios II Processor Reference Handbook and the
Guide.
Description
Nios II Processor Reference Handbook
Processor
Nios II Custom
3–59