IPR-NIOS Altera, IPR-NIOS Datasheet - Page 49

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Memory Management Unit
Memory Management Unit
December 2010 Altera Corporation
Recommended Usage
Memory Management
1
The Nios II MPU supervisor and user memory divisions are determined by the
operating system or runtime environment. The MPU provides user access
permissions on a region basis. Refer to
information about MPU regions.
The Nios II processor provides an MMU to support full-featured operating systems.
Operating systems that require virtual memory rely on an MMU to manage the
virtual memory. When present, the MMU manages memory accesses including
translation of virtual addresses to physical addresses, memory protection, cache
control, and software process memory allocation.
Including the Nios II MMU in your Nios II hardware system is optional. The MMU is
only useful with an operating system that takes advantage of it.
Many Nios II systems have simpler requirements where minimal system software or a
small-footprint operating system (such as the Altera
(HAL) or a third party real-time operating system) is sufficient. Such software is
unlikely to function correctly in a hardware system with an MMU-based Nios II
processor. Do not include an MMU in your Nios II system unless your operating
system requires it.
The Altera HAL and HAL-based real-time operating systems do not support the
MMU.
If your system needs memory protection, but not virtual memory management, refer
to
Memory management comprises two key functions:
■
■
Virtual Addressing
A virtual address is the address that software uses. A physical address is the address
which the hardware outputs on the address lines of the Avalon
MMU divides virtual memory into 4 kilobyte (KB) pages and physical memory into
4 KB frames.
The MMU contains a hardware translation lookaside buffer (TLB). The operating
system is responsible for creating and maintaining a page table (or equivalent data
structures) in memory. The hardware TLB acts as a software managed cache for the
page table. The MMU does not perform any operations on the page table, such as
hardware table walks. Therefore the operating system is free to implement its page
table in any appropriate manner.
“Memory Protection Unit” on page
Virtual addressing—Mapping a virtual memory space into a physical memory
space
Memory protection—Allowing access only to certain memory under certain
conditions
3–8.
“Memory Regions” on page 3–8
®
hardware abstraction library
Nios II Processor Reference Handbook
®
bus. The Nios II
for more
3–3