IPR-NIOS Altera, IPR-NIOS Datasheet - Page 51

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Memory Management Unit
Table 3–2. Virtual Memory Partitions (Part 2 of 2)
December 2010 Altera Corporation
User
Note to
(1) Supervisor-only partition
Partition
Table
3–2:
1
0x00000000–0x7FFFFFFF
Each partition has a specific size, purpose, and relationship to the TLB:
■
■
■
■
I/O and kernel partitions bypass the TLB. The kernel MMU and user partitions use
the TLB. If all software runs in the kernel partition, the MMU is effectively disabled.
Physical Memory Address Space
The 4-GB physical memory is divided into low memory and high memory. The lowest
½ GB of physical address space is low memory. The upper 3½ GB of physical address
space is high memory.
Figure 3–1. Division of Physical Memory
High physical memory can only be accessed through the TLB. Any physical address
in low memory (29-bits or less) can be accessed through the TLB or by bypassing the
TLB. When bypassing the TLB, a 29-bit physical address is computed by clearing the
top three bits of the 32-bit virtual address.
To function correctly, the base physical address of all exception vectors (reset, general
exception, break, and fast TLB miss) must point to low physical memory so that
hardware can correctly map their virtual addresses into the kernel partition. This
restriction is enforced by the Nios II Processor parameter editor in SOPC Builder.
Virtual Address Range
The 512-megabyte (MB) I/O partition provides access to peripherals.
The 512-MB kernel partition provides space for the operating system kernel.
The 1-GB kernel MMU partition is used by the TLB miss handler and kernel
processes.
The 2-GB user partition is used by application processes.
0xFFFFFFFF
0x20000000
0x1FFFFFFF
0x00000000
Figure 3–1
3.5 GByte High Memory
0.5 GByte Low Memory
processes
Used By
User
shows how physical memory is divided.
Memory Access
Uses TLB
Accessed directly or via TLB
Accessed only via TLB
Nios II Processor Reference Handbook
User Mode
Set by TLB
Access
Default Data
Cacheability
Set by TLB
3–5