IPR-NIOS Altera, IPR-NIOS Datasheet - Page 73

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Registers
Table 3–31. sstatus Control Register Fields
Table 3–32. sstatus Control Register Field Descriptions (Part 1 of 2)
December 2010 Altera Corporation
31
SRS
RSIE
NMI
PRS
Bit
30
29
SRS is the switched register set bit. The processor sets SRS to 1 when
an external interrupt occurs, if the interrupt required the processor to
switch to a different register set.
28
Reserved
f
f
1
27
26
When shadow register sets are implemented, status.CRS indicates the register set
currently in use. A Nios II core can have up to 63 shadow register sets. If n is the
configured number of shadow register sets, the shadow register sets are numbered
from 1 to n. Register set 0 is the normal register set.
A shadow register set behaves precisely the same as the normal register set. The
register set currently in use can only be determined by examining status.CRS.
When shadow register sets and the EIC interface are implemented on the Nios II core,
you must ensure that your software is built with the Nios II EDS version 9.0 or later.
Earlier versions have an implementation of the eret instruction that is incompatible
with shadow register sets.
Shadow register sets are typically used in conjunction with the EIC interface. This
combination can substantially reduce interrupt latency.
For details of EIC interface usage, refer to
System software can read from and write to any shadow register set by setting
status.PRS and using the rdprs and wrprs instructions.
For details of the rdprs and wrprs instructions, refer to the
chapter of the Nios II Processor Reference Handbook.
The sstatus Register
The value in the sstatus register preserves the state of the Nios II processor during
external interrupt handling. The value of sstatus is undefined at processor reset.
Some bits are exclusively used by and available only to certain features of the
processor.
The sstatus register is physically stored in general-purpose register r30 in each
shadow register set. The normal register set does not have an sstatus register, but
each shadow register set has a separate sstatus register.
Table 3–32
25
24
23
22
Table 3–31
gives details of the fields defined in the sstatus register.
Description
21
20
(1)
(1)
(1)
19
PRS
shows the layout of the sstatus register.
18
17
16
15
14
13
CRS
“Exception Processing” on page
12
11
10
Read/Write
Read/Write
Read/Write
Read/Write
Access
9
8
Nios II Processor Reference Handbook
Instruction Set Reference
7
IL
Undefined
Undefined
Undefined
Undefined
6
Reset
5
4
EIC interface
register sets
3
and shadow
3–30.
Available
2
only
(1)
(1)
(1)
1
3–27
0