IPR-NIOS Altera, IPR-NIOS Datasheet - Page 121

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Instantiating the Nios II Processor in SOPC Builder
MMU and MPU Settings Page
December 2010 Altera Corporation
MMU
MPU
f
1
When Include MMU on the Core Nios II page is on, the MMU settings on the MMU
and MPU Settings page provide the following options for the MMU in the Nios II/f
core. Typically, you should not need to change any of these settings from their default
values.
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For details on the MMU, refer to the
Reference Handbook. For specifics on the Nios II/f core, refer to the
Implementation Details
When Include MPU on the Core Nios II page is on, the MPU settings on the MMU
and MPU Settings page provide the following options for the MPU in the Nios II/f
core.
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The maximum region size is the size of the Nios II instruction and data addresses
automatically determined when the Nios II system is generated in SOPC Builder.
Maximum region size is based on the address range of slaves connected to the Nios II
instruction and data masters.
Process ID (PID) Bits—Specifies the number of bits to use to represent the process
identifier.
Optimize number of TLB entries based on device family—When on, specifies
the optimal number of TLB entries to allocate based on the device family of the
target hardware and disables TLB Entries.
TLB Entries—Specifies the number of entries in the translation lookaside buffer
(TLB).
TLB Set-Associativity—Specifies the number of set-associativity ways in the TLB.
Micro ITLB Entries—Specifies the number of entries in the micro instruction TLB.
Micro DTLB Entries—Specifies the number of entries in the micro data TLB.
Use Limit for Region Range—Controls whether the amount of memory in the
region is defined by size or by upper address limit. When on, the amount of
memory is based on the given upper address limit. When off, the amount of
memory is based on the given size.
Number of Data Regions—Specifies the number of data regions to allocate.
Allowed values range from 2 to 32.
Minimum Data Region Size—Specifies the minimum data region size. Allowed
values range from 64 bytes to 1 megabyte (MB) and must be a power of two.
Number of Instruction Regions—Specifies the number of instruction regions to
allocate. Allowed values range from 2 to 32.
Minimum Instruction Region Size—Specifies the minimum instruction region
size. Allowed values range from 64 bytes to 1 MB and must be a power of two.
chapter of the Nios II Processor Reference Handbook.
Programming Model
chapter of the Nios II Processor
Nios II Processor Reference Handbook
Nios II Core
4–13