IPR-NIOS Altera, IPR-NIOS Datasheet - Page 77

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Exception Processing
December 2010 Altera Corporation
Exception Overview
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Each of the Nios II exceptions falls into one of the following categories:
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Exception—a transfer of control away from a program’s normal flow of execution,
caused by an event, either internal or external to the processor, which requires
immediate attention.
Interrupt—an exception caused by an explicit request signal from an external
device; also: hardware interrupt.
Interrupt controller—hardware that interfaces the processor to interrupt request
signals from external devices.
Internal interrupt controller—the nonvectored interrupt controller that is integral
to the Nios II processor. The internal interrupt controller is available in all
revisions of the Nios II processor.
Vectored interrupt controller (VIC)—an Altera-provided external interrupt
controller.
Exception (interrupt) latency—The time elapsed between the event that causes the
exception (assertion of an interrupt request) and the execution of the first
instruction at the handler address.
Exception (interrupt) response time—The time elapsed between the event that
causes the exception (assertion of an interrupt request) and the execution of
nonoverhead exception code, that is, specific to the exception type (device).
Global interrupts—All maskable exceptions on the Nios II processor, including
internal interrupts and maskable external interrupts, but not including
nonmaskable interrupts.
Worst-case latency—The value of the exception (interrupt) latency, assuming the
maximum disabled time or maximum masked time, and assuming that the
exception (interrupt) occurs at the beginning of the masked/disabled time.
Maximum disabled time—The maximum amount of continuous time that the
system spends with maskable interrupts disabled.
Maximum masked time—The maximum amount of continuous time that the
system spends with a single interrupt masked.
Shadow register set—a complete alternate set of Nios II general-purpose registers,
which can be used to maintain a separate runtime context for an ISR.
Reset exception—Occurs when the Nios II processor is reset. Control is transferred
to the reset address you specify in the Nios II processor IP core setup parameters.
Break exception—Occurs when the JTAG debug module requests control. Control
is transferred to the break address you specify in the Nios II processor IP core
setup parameters.
Interrupt exception—Occurs when a peripheral device signals a condition
requiring service
Instruction-related exception—Occurs when any of several internal conditions
occurs, as detailed in
exception address you specify in the Nios II processor IP core setup parameters.
Table 3–33 on page
3–32. Control is transferred to the
Nios II Processor Reference Handbook
3–31