IPR-NIOS Altera, IPR-NIOS Datasheet - Page 151

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Nios II Core Implementation Details
Nios II/s Core
December 2010 Altera Corporation
Instruction Performance
Exception Handling
All instructions take one or more cycles to execute. Some instructions have other
penalties associated with their execution. Instructions that flush the pipeline cause up
to three instructions after them to be cancelled. This creates a three-cycle penalty and
an execution time of four cycles. Instructions that require an Avalon-MM transfer are
stalled until the transfer completes.
Execution performance for all instructions is shown in
Table 5–15. Instruction Execution Performance for Nios II/s Core
The Nios II/s core supports the following exception types:
■
■
■
■
Normal ALU instructions (e.g., add, cmplt)
Combinatorial custom instructions
Multi-cycle custom instructions
Branch (correctly predicted taken)
Branch (correctly predicted not taken)
Branch (mispredicted)
trap, break, eret, bret,
flushp, wrctl, unimplemented
jmp, jmpi, ret, call, callr
rdctl
load, store
flushi, initi
Multiply
Divide
Shift/rotate (with hardware multiply using embedded
multipliers)
Shift/rotate (with hardware multiply using LE-based multipliers)
Shift/rotate (without hardware multiply present)
All other instructions
Note to
(1) Depends on the hardware multiply or divide option. Refer to
Internal hardware interrupt
Software trap
Illegal instruction
Unimplemented instruction
Table
5–15:
Instruction
Table 5–12 on page 5–16
Table
Nios II Processor Reference Handbook
Cycles
1 to 32
5–15.
> 1
> 1
(1)
(1)
1
1
2
1
4
4
4
1
4
3
4
1
for details.
Pipeline flush
Pipeline flush
Pipeline flush
Penalties
5–19