IPR-NIOS Altera, IPR-NIOS Datasheet - Page 72

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–26
Nios II Processor Reference Handbook
Shadow Register Sets
1
1
The PERM Field
The PERM field specifies the allowed access permissions.
values of the PERM field for instruction regions and
of the PERM field for data regions.
Table 3–29. Instruction Region Permission Values
Table 3–30. Data Region Permission Values
Unlisted table values are reserved and must not be used. If you use reserved values,
the resulting behavior is undefined.
The RD Flag
Setting the RD flag signifies that an MPU region read operation should be performed
when a wrctl instruction is issued to the mpuacc register. Refer to
and Write Operations” on page 3–29
0 when read by a rdctl instruction.
The WR Flag
Setting the WR flag signifies that an MPU region write operation should be performed
when a wrctl instruction is issued to the mpuacc register. Refer to
and Write Operations” on page 3–29
0 when read by a rdctl instruction.
Setting both the RD and WR flags to one results in undefined behavior.
The Nios II processor can optionally have one or more shadow register sets. A
shadow register set is a complete alternate set of Nios II general-purpose registers,
which can be used to maintain a separate runtime context for an interrupt service
routine (ISR).
Value
Value
0
1
2
0
1
2
4
5
6
Supervisor Permissions
Supervisor Permissions
for more information. The RD flag always returns
for more information. The WR flag always returns
Read/Write
Read/Write
Read/Write
Execute
Execute
None
None
Read
Read
Table 3–30
Table 3–29
December 2010 Altera Corporation
shows possible values
Chapter 3: Programming Model
User Permissions
User Permissions
“MPU Region Read
“MPU Region Read
Read/Write
shows possible
Execute
None
None
None
None
Read
None
Read
Registers