IPR-NIOS Altera, IPR-NIOS Datasheet - Page 192

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

8–6
Nios II Processor Reference Handbook
f
Table 8–5. Notation Conventions (Part 2 of 2)
The following exceptions are not listed for each instruction because they can occur on
any instruction fetch:
■
■
■
■
■
For details on these and all Nios II exceptions, refer to the
of the Nios II Processor Reference Handbook.
X | Y
X ^ Y
~X
Mem8[X]
Mem16[X]
Mem32[X]
label
(signed) rX
(unsigned) rX
Note to
(1) All register operations apply to the current register set, except as noted.
Supervisor-only instruction address
Fast TLB miss (instruction)
Double TLB miss (instruction)
TLB permission violation (execute)
MPU region violation (instruction)
Notation
Table
8–5:
Bitwise logical OR
Bitwise logical XOR
Bitwise logical NOT (one’s complement)
The byte located in data memory at byte address X
The halfword located in data memory at byte address X
The word located in data memory at byte address X
An address label specified in the assembly file
The value of rX treated as a signed number
The value of rX treated as an unsigned number
Meaning
Chapter 8: Instruction Set Reference
Programming Model
December 2010 Altera Corporation
Instruction Set Reference
chapter