IPR-NIOS Altera, IPR-NIOS Datasheet - Page 150

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–18
Nios II Processor Reference Handbook
The Nios II/s core employs a 5-stage pipeline. The pipeline stages are listed in
Table
Table 5–14. Implementation Pipeline Stages for Nios II/s Core
Up to one instruction is dispatched and/or retired per cycle. Instructions are
dispatched and retired in-order. Static branch prediction is implemented using the
branch offset direction; a negative offset (backward branch) is predicted as taken, and
a positive offset (forward branch) is predicted as not-taken. The pipeline stalls for the
following conditions:
■
■
■
■
Pipeline Stalls
The pipeline is set up so that if a stage stalls, no new values enter that stage or any
earlier stages. No “catching up” of pipeline stages is allowed, even if a pipeline stage
is empty.
Only the M-stage is allowed to create stalls.
The M-stage stall occurs if any of the following conditions occurs:
■
■
■
■
Branch Prediction
The Nios II/s core performs static branch prediction to minimize the cycle penalty
associated with taken branches.
Multi-cycle instructions (e.g., shift/rotate without hardware multiply)
Avalon-MM instruction master port read accesses
Avalon-MM data master port read/write accesses
Data dependencies on long latency instructions (e.g., load, multiply, shift
operations)
An M-stage load/store instruction is waiting for Avalon-MM data master transfer
to complete.
An M-stage shift/rotate instruction is still performing its operation when using
the multi-cycle shift circuitry (i.e., when the hardware multiplier is not available).
An M-stage shift/rotate/multiply instruction is still performing its operation
when using the hardware multiplier (which takes three cycles).
An M-stage multi-cycle custom instruction is asserting its stall signal. This only
occurs if the design includes multi-cycle custom instructions.
5–14.
Stage Letter
M
W
D
F
E
Chapter 5: Nios II Core Implementation Details
Stage Name
Writeback
Memory
Execute
Decode
Fetch
December 2010 Altera Corporation
Nios II/s Core