IPR-NIOS Altera, IPR-NIOS Datasheet - Page 71

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Registers
December 2010 Altera Corporation
1
Table 3–28. MASK Region Size Encodings (Part 2 of 2)
Bit 31 of the mpuacc register is not used by the MASK field. Because memory region size
is already a power of two, one less bit is needed. The MASK field contains the following
value, where region_size is in bytes:
MASK = 0x1FFFFFF << log2(region_size >> 6)
The LIMIT Field
When the amount of memory reserved for a region is defined by an upper address
limit, the LIMIT field specifies the upper address of the memory region plus one. For
example, to achieve a memory range for byte addresses 0x4000 to 0x4fff with a 256
byte minimum region size, the BASE field of the mpubase register is set to 0x40 (0x4000
>> 8) and the LIMIT field is set to 0x50 (0x5000 >> 8). Because the LIMIT field is one
more bit than the number of bits of the BASE field of the mpubase register, bit 31 of the
mpuacc register is available to the LIMIT field.
The C Flag
The C flag determines the default data cacheability of an MPU region. The C flag only
applies to data regions. For instruction regions, the C bit must be written with 0 and is
always read as 0.
When data cacheability is enabled on a data region, a data access to that region can be
cached, if a data cache is present in the system. You can override the default
cacheability and force an address to noncacheable with an ldio or stio instruction.
The bit 31 cache bypass feature is supported when the MPU is present. Refer to
“Cache Memory” on page 3–53
MASK Encoding
0x1E00000
0x1C00000
0x1800000
0x1000000
0x0000000
for more information on cache bypass.
Nios II Processor Reference Handbook
Region Size
128 MB
256 MB
512 MB
1 GB
2 GB
3–25