IPR-NIOS Altera, IPR-NIOS Datasheet - Page 91

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Exception Processing
Table 3–34. Conditions Required to Take External Interrupt
December 2010 Altera Corporation
Note to
(1) Nested interrupts using the same register set are allowed only if system software has explicitly permitted them by setting status.RSIE. This
status.NMI
restriction ensures that such interrupts are taken only if the handler is coded to save the register context.
== 0
Yes
Table
RNMI == 1
3–34:
status.NMI
== 1
No
Table 3–34
external interrupt.
The Nios II processor supports fast nested interrupts with shadow register sets, as
described in
implemented, the config.ANI field is set to 0 at reset.
Software must set config.ANI to 1 to enable fast nested interrupts. If config.ANI is set
to 1 when a maskable external interrupt occurs, status.PIE not cleared. Leaving
status.PIE set allows higher level interrupts to be taken immediate, without
requiring the interrupt handler to set status.PIE to 1.
System software can disable fast nested interrupts by setting config.ANI to 0. In this
state, the processor disables maskable interrupts when taking an exception, just as it
does without shadow register sets. An individual interrupt handler can re-enable
interrupts by setting status.PIE to 1, if desired.
Exception Flow with the Internal Interrupt Controller
A general exception handler determines which of the pending interrupts has the
highest priority, and then transfers control to the appropriate ISR. The ISR stops the
interrupt from being visible (either by clearing it at the source or masking it using
ienable) before returning and/or before re-enabling PIE. The ISR also saves estatus
and ea (r29) before re-enabling PIE.
Interrupts can be re-enabled by writing one to the PIE bit, thereby allowing the
current ISR to be interrupted. Typically, the exception routine adjusts ienable so that
IRQs of equal or lower priority are disabled before re-enabling interrupts. Refer to
“Handling Nested Exceptions” on page 3–48
status.PIE
== 0
summarizes the conditions under which the Nios II processor takes an
No
“Shadow Register Sets” on page
status.IL
RIL <=
No
status.RSIE
No
Processor Has Shadow Register Sets
== 0
RRS == status.CRS
(1)
RNMI == 0
for more information.
3–26. When shadow register sets are
status.PIE == 1
status.RSIE
== 1
Yes
RIL > status.IL
Nios II Processor Reference Handbook
status.CRS
RRS !=
Yes
No Shadow
Register
Sets
Yes
3–45