IPR-NIOS Altera, IPR-NIOS Datasheet - Page 152

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–20
Nios II/e Core
Nios II Processor Reference Handbook
JTAG Debug Module
Overview
Arithmetic Logic Unit
The Nios II/s core supports the JTAG debug module to provide a JTAG interface to
software debugging tools. The Nios II/s core supports an optional enhanced interface
that allows real-time trace data to be routed out of the processor and stored in an
external debug probe.
The Nios II/e economy core is designed to achieve the smallest possible core size.
Altera designed the Nios II/e core with a singular design goal: reduce resource
utilization any way possible, while still maintaining compatibility with the Nios II
instruction set architecture. Hardware resources are conserved at the expense of
execution performance. The Nios II/e core is roughly half the size of the Nios II/s
core, but the execution performance is substantially lower.
The resulting core is optimal for cost-sensitive applications as well as applications that
require simple control logic.
The Nios II/e core:
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The following sections discuss the noteworthy details of the Nios II/e core
implementation. This document does not discuss low-level design issues, or
implementation details that do not affect Nios II hardware or software designers.
The Nios II/e core does not provide hardware support for any of the potential
unimplemented instructions. All unimplemented instructions are emulated in
software.
The Nios II/e core employs dedicated shift circuitry to perform shift and rotate
operations. The dedicated shift circuitry achieves one-bit-per-cycle shift and rotate
operations.
Executes at most one instruction per six clock cycles
Can access up to 2 GB of external address space
Supports the addition of custom instructions
Supports the JTAG debug module
Does not provide hardware support for potential unimplemented instructions
Has no instruction cache or data cache
Does not perform branch prediction
Chapter 5: Nios II Core Implementation Details
December 2010 Altera Corporation
Nios II/e Core