IPR-NIOS Altera, IPR-NIOS Datasheet - Page 55

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Memory Protection Unit
December 2010 Altera Corporation
Base Address
The base address specifies the lowest address of the region. The base address is
aligned on a region-sized boundary. For example, a 4 KB region must have a base
address that is a multiple of 4 KB. If the base address is not properly aligned, the
behavior is undefined.
Region Type
Each region is identified as either an instruction region or a data region.
Region Index
Each region has an index ranging from zero to the number of regions of its region type
minus one. Index zero has the highest priority.
Region Size or Upper Address Limit
An SOPC Builder generation-time option controls whether the amount of memory in
the region is defined by size or upper address limit. The size is an integer power of
two bytes. The limit is the highest address of the region plus one. The minimum
supported region size is 64 bytes but can be configured at system generation time for
larger minimum sizes to save logic resources. The maximum supported region size
equals the Nios II address space (a function of the address ranges of slaves connected
to the Nios II masters). Any access outside of the Nios II address space is considered
not to match any region and triggers an MPU region violation exception.
When regions are defined by size, the size is encoded as a binary mask to facilitate the
following MPU region address range matching:
(address & region_mask) == region_base_address
When regions are defined by limit, the limit is encoded as an unsigned integer to
facilitate the following MPU region address range matching:
(address >= region_base) && (address < region_limit)
The region limit uses a less-than instead of a less-than-or-equal-to comparison
because less-than provides a more efficient implementation. The limit is one bit larger
than the address so that full address range may be included in a range. Defining the
region by limit results in slower and larger address range match logic than defining
by size but allows finer granularity in region sizes.
Access Permissions
The access permissions consist of execute permissions for instruction regions and
read/write permissions for data regions. Any instruction that performs a memory
access that violates the access permissions triggers an exception. Additionally, any
instruction that performs a memory access that does not match any region triggers an
exception.
Nios II Processor Reference Handbook
3–9