IPR-NIOS Altera, IPR-NIOS Datasheet - Page 248
IPR-NIOS
Manufacturer Part Number
IPR-NIOS
Description
IP NIOS II MEGACORE RENEW
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-NIOS.pdf
(294 pages)
Specifications of IPR-NIOS
License
Renewal License
Lead Free Status / RoHS Status
Not applicable / Not applicable
- Current page: 248 of 294
- Download datasheet (3Mb)
8–62
ldh / ldhio
Nios II Processor Reference Handbook
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
31
30
30
29
29
A
A
28
28
27
27
26
26
25
25
rB ← σ (Mem16[rA + σ (IMM16)])
ldh rB, byte_offset(rA)
ldhio rB, byte_offset(rA)
ldh r6, 100(r5)
Computes the effective byte address specified by the sum of rA and the instruction's signed
16-bit immediate value. Loads register rB with the memory halfword located at the effective byte
address, sign extending the 16-bit value to 32 bits. The effective byte address must be halfword
aligned. If the byte address is not a multiple of 2, the operation is undefined.
In processors with a data cache, this instruction may retrieve the desired data from the cache
instead of from memory. Use the ldhio instruction for peripheral I/O. In processors with a data
cache, ldhio bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. In
processors without a data cache, ldhio acts like ldh.
For more information on data cache, refer to the
the Nios II Software Developer’s Handbook.
■
■
■
■
■
■
I
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
24
24
B
B
Supervisor-only data address
Misaligned data address
TLB permission violation (read)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
23
23
22
22
21
21
20
20
19
19
Instruction format for ldhio
Instruction format for ldh
18
18
17
17
16
16
load halfword from memory or I/O peripheral
15
15
IMM16
IMM16
14
14
13
13
12
12
Cache and Tightly Coupled Memory
11
11
10
10
9
9
8
8
Chapter 8: Instruction Set Reference
December 2010 Altera Corporation
7
7
6
6
5
5
Instruction Set Reference
4
4
0x0f
0x2f
3
3
chapter of
2
2
1
1
0
0
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