IPR-NIOS Altera, IPR-NIOS Datasheet - Page 37

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Processor Architecture
Memory and I/O Organization
December 2010 Altera Corporation
Tightly-Coupled Memory
f
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Optimal cache configuration is application specific, although you can make decisions
that are effective across a range of applications. For example, if a Nios II processor
system includes only fast, on-chip memory (i.e., it never accesses slow, off-chip
memory), an instruction or data cache is unlikely to offer any performance gain. As
another example, if the critical loop of a program is 2 kilobytes (KB), but the size of the
instruction cache is 1 KB, an instruction cache does not improve execution speed. In
fact, an instruction cache may degrade performance in this situation.
If an application always requires certain data or sections of code to be located in cache
memory for performance reasons, the tightly-coupled memory feature might provide
a more appropriate solution. Refer to
details.
Cache Bypass Methods
The Nios II architecture provides the following methods for bypassing the data cache:
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I/O Load and Store Instructions Method
The load and store I/O instructions such as ldio and stio bypass the data cache and
force an Avalon-MM data transfer to a specified address.
The Bit-31 Cache Bypass Method
The bit-31 cache bypass method on the data master port uses bit 31 of the address as a
tag that indicates whether the processor should transfer data to/from cache, or bypass
it. This is a convenience for software, which might need to cache certain addresses
and bypass others. Software can pass addresses as parameters between functions,
without having to specify any further information about whether the addressed data
is cached or not.
To determine which cores implement which cache bypass methods, refer to the
Core Implementation Details
Tightly-coupled memory provides guaranteed low-latency memory access for
performance-critical applications. Compared to cache memory, tightly-coupled
memory provides the following benefits:
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The largest block of performance-critical data is smaller than the data cache
I/O load and store instructions
Bit-31 cache bypass
Performance similar to cache memory
Software can guarantee that performance-critical code or data is located in
tightly-coupled memory
No real-time caching overhead, such as loading, invalidating, or flushing memory
chapter of the Nios II Processor Reference Handbook.
“Tightly-Coupled Memory” on page 2–15
Nios II Processor Reference Handbook
Nios II
for
2–15