IPR-NIOS Altera, IPR-NIOS Datasheet - Page 81

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Exception Processing
December 2010 Altera Corporation
Interrupt Exceptions
1
The processor enters the break processing state under either of the following
conditions:
■
■
Processing a Break
A break causes the processor to take the following steps:
1. Stores the contents of the status register to bstatus.
2. Clears status.PIE to zero, disabling maskable interrupts.
3. Writes the address of the instruction following the break to the ba register (r30) in
4. Clears status.U to zero, forcing the processor into supervisor mode, when the
5. Sets status.EH to one, indicating the processor is handling an exception, when the
6. Copies status.CRS to status.PRS and then sets status.CRS to 0.
7. Transfers execution to the break handler, stored at the break vector specified at
All noninterrupt exception handlers, including the break handler, must run in the
normal register set.
Understanding Register Usage
The bstatus control register and general-purpose registers bt (r25) and ba (r30) in the
normal register set are reserved for debugging. Code is not prevented from writing to
these registers, but debug code might overwrite the values. The break handler can use
bt (r25) to help save additional registers.
Returning From a Break
After processing a break, the break handler releases control of the processor by
executing a bret instruction. The bret instruction restores status by copying the
contents of bstatus and returns program execution to the address in the ba register
(r30) in the normal register set. Aside from bt and ba, all registers are guaranteed to
be returned to their pre-break state after returning from the break handler.
A peripheral device can request an interrupt by asserting an interrupt request (IRQ)
signal. IRQs interface to the Nios II processor through an interrupt controller. You can
configure the Nios II processor with either of the following interrupt controller
options:
The processor executes the break instruction. This is often referred to as a software
break.
The JTAG debug module asserts a hardware break.
1
the normal register set.
system contains an MMU or MPU.
system contains an MMU.
system generation time.
Nonmaskable interrupts (NMIs) are not affected by status.PIE, and can be
taken while processing a break exception.
Nios II Processor Reference Handbook
3–35