IPR-NIOS Altera, IPR-NIOS Datasheet - Page 138

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–6
Table 5–4. Hardware Multiply and Divide Details for the Nios II/f Core
Nios II Processor Reference Handbook
No hardware multiply or
divide
Logic elements
DSP block on Stratix II
and Stratix III families
Embedded multipliers on
Cyclone II and
Cyclone III families
Hardware divide
ALU Option
1
The Nios II/f core also provides a hardware divide option that includes LE-based
divide circuitry in the ALU.
Including an ALU option improves the performance of one or more arithmetic
instructions.
The performance of the embedded multipliers differ, depending on the target FPGA
family.
Table 5–4
The cycles per instruction value determines the maximum rate at which the ALU can
dispatch instructions and produce each result. The latency value determines when the
result becomes available. If there is no data dependency between the results and
operands for back-to-back instructions, then the latency does not affect throughput.
However, if an instruction depends on the result of an earlier instruction, then the
processor stalls through any result latency cycles until the result is ready.
In the following code example, a multiply operation (with 1 instruction cycle and 2
result latency cycles) is followed immediately by an add operation that uses the result
of the multiply. On the Nios II/f core, the addi instruction, like most ALU
instructions, executes in a single cycle. However, in this code example, execution of
the addi instruction is delayed by two additional cycles until the multiply operation
completes.
mul r1, r2, r3
addi r1, r1, 100
In contrast, the following code does not stall the processor.
mul r1, r2, r3
or r5, r5, r6
or r7, r7, r8
addi r1, r1, 100
Multiply and divide
instructions generate an
exception
ALU includes 32 x 4-bit
multiplier
ALU includes 32 x 32-bit
multiplier
ALU includes 32 x 16-bit
multiplier
ALU includes multicycle
divide circuit
Hardware Details
lists the details of the hardware multiply and divide options.
; r1 = r2 * r3
; r1 = r1 + 100 (Depends on result of mul)
; r1 = r2 * r3
; No dependency on previous results
; No dependency on previous results
; r1 = r1 + 100 (Depends on result of mul)
Instruction
Cycles per
4 – 66
11
–
1
5
Result Latency
Chapter 5: Nios II Core Implementation Details
Cycles
+2
+2
+2
+2
–
December 2010 Altera Corporation
mul, muli, mulxss,
mulxsu, mulxuu
Instructions
Supported
mul, muli
mul, muli
div, divu
None
Nios II/f Core