IPR-NIOS Altera, IPR-NIOS Datasheet - Page 95

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Exception Processing
December 2010 Altera Corporation
f
1
For details about when the Nios II processor takes exceptions, refer to
Processing Flow” on page
to the
details about MMU and MPU exceptions, refer to
page
A system can be designed to eliminate the possibility of nested exceptions. However,
if nested exceptions are possible, the exception handlers must be carefully written to
prevent each handler from corrupting the context in which a pre-empted handler
runs.
If an exception handler issues a trap instruction, an optional instruction, or an
instruction which could generate an MMU or MPU exception, it must save and restore
the contents of the estatus and ea registers.
Nested Exceptions with the Internal Interrupt Controller
You can enable nested exceptions in each exception handler on a case-by-case basis. If
you want to allow a given exception handler to be pre-empted, set status.PIE to 1
near the beginning of the handler. Enabling maskable interrupts early in the handler
minimizes the worst-case latency of any nested exceptions.
Ensure that all pre-empting handlers preserve the register contents.
Nested Exceptions with an External Interrupt Controller
With an EIC, handling of nested interrupts is more sophisticated than with the
internal interrupt controller. Handling of noninterrupt exceptions, however, is the
same.
When individual external interrupts have dedicated shadow register sets, the Nios II
processor supports fast interrupt handling with no overhead for saving register
contents. To take full advantage of fast interrupt handling, system software must set
up certain conditions. With the following conditions satisfied, ISRs need not save and
restore register contents on entry and exit:
■
■
■
Automatic nested interrupts are enabled (config.ANI is set to 1).
Each interrupt is assigned to a dedicated shadow register set
All interrupts with the same RIL are assigned to dedicated shadow register sets.
3–39.
Processor Architecture
3–43. For details about unimplemented instructions, refer
chapter of the Nios II Processor Reference Handbook. For
“Instruction-Related Exceptions” on
Nios II Processor Reference Handbook
“Exception
3–49