IPR-NIOS Altera, IPR-NIOS Datasheet - Page 279

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Instruction Set Reference
Instruction Set Reference
stb / stbio
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
31
30
30
29
29
A
A
28
28
27
27
26
26
25
25
24
24
B
B
Mem8[rA + σ (IMM16)] ← rB
stb rB, byte_offset(rA)
stbio rB, byte_offset(rA)
stb r6, 100(r5)
Computes the effective byte address specified by the sum of rA and the instruction's signed
16-bit immediate value. Stores the low byte of rB to the memory byte specified by the effective
address.
In processors with a data cache, this instruction may not generate an Avalon-MM bus cycle to
noncache data memory immediately. Use the stbio instruction for peripheral I/O. In
processors with a data cache, stbio bypasses the cache and is guaranteed to generate an
Avalon-MM data transfer. In processors without a data cache, stbio acts like stb.
Supervisor-only data address
Misaligned data address
TLB permission violation (write)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
I
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
23
23
22
22
21
21
20
20
19
19
Instruction format for stbio
Instruction format for stb
18
18
17
17
16
16
7..0
15
15
IMM16
IMM16
14
14
store byte to memory or I/O peripheral
13
13
12
12
11
11
10
10
9
9
8
8
Nios II Processor Reference Handbook
7
7
6
6
5
5
4
4
0x05
0x25
3
3
2
2
1
1
8–93
0
0