IPR-NIOS Altera, IPR-NIOS Datasheet - Page 15

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

© 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
NII51001-10.1.0
Introduction
Nios II Processor System Basics
Nios II Processor Reference Handbook
December 2010
December 2010
NII51001-10.1.0
f
This handbook is the primary reference for the Nios
processors. The handbook describes the Nios II processor from a high-level
conceptual description to the low-level details of implementation. The chapters in this
handbook define the Nios II processor architecture, the programming model, the
instruction set, and more.
This handbook is part of a larger collection of documents covering the Nios II
processor and its usage that you can find on the
the Altera
This handbook assumes you have a basic familiarity with embedded processor
concepts. You do not need to be familiar with any specific Altera technology or with
Altera development tools. This handbook intentionally minimizes discussion of
hardware implementation details of the processor system. That said, the Nios II
processors are designed for Altera FPGA devices, and so this handbook does describe
some FPGA implementation concepts. Your familiarity with FPGA technology
provides a deeper understanding of the engineering trade-offs related to the design
and implementation of the Nios II processor.
This Introduction chapter introduces the Altera Nios II embedded processor family.
The chapter helps hardware and software engineers understand the similarities and
differences between the Nios II processor and traditional embedded processors. This
chapter contains the following sections:
■
■
■
■
■
The Nios II processor is a general-purpose RISC processor core, providing:
■
■
■
■
■
■
“Nios II Processor System Basics”
“Getting Started with the Nios II Processor” on page 1–2
“Customizing Nios II Processor Designs” on page 1–3
“Configurable Soft-Core Processor Concepts” on page 1–4
“OpenCore Plus Evaluation” on page 1–5
Full 32-bit instruction set, data path, and address space
32 general-purpose registers
Optional shadow register sets
32 interrupt sources
External interrupt controller interface for more interrupt sources
Single-instruction 32 × 32 multiply and divide producing a 32-bit result
®
website.
Literature: Nios II Processor
®
II family of embedded
1. Introduction
page on
Subscribe