IPR-NIOS Altera, IPR-NIOS Datasheet - Page 237

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Instruction Set Reference
Instruction Set Reference
flushd
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
A
28
27
26
25
24
0
Flushes the data cache line associated with address rA + σ (IMM16).
flushd IMM16(rA)
flushd -100(r6)
If the Nios II processor implements a direct mapped data cache, flushd writes the data cache
line that is mapped to the specified address back to memory if the line is dirty, and then clears
the data cache line. Unlike flushda, flushd writes the dirty data back to memory even when
the addressed data is not currently in the cache. This process comprises the following steps:
■
■
■
■
■
If the Nios II processor core does not have a data cache, the flushd instruction performs no
operation.
Use flushd to write dirty lines back to memory even if the addressed memory location is not in
the cache, and then flush the cache line. By contrast, refer to
address” on page
cache address” on page 8–56
For more information on data cache, refer to the
the Nios II Software Developer’s Handbook.
None
I
A = Register index of operand rA
IMM16 = 16-bit signed immediate value
Compute the effective address specified by the sum of rA and the signed 16-bit immediate
value.
Identify the data cache line associated with the computed effective address. Each data cache
effective address comprises a tag field and a line field. When identifying the data cache
line, flushd ignores the tag field and only uses the line field to select the data cache line
to clear.
Skip comparing the cache line tag with the effective address to determine if the addressed
data is currently cached. Because flushd ignores the cache line tag, flushd flushes the
cache line regardless of whether the specified data location is currently cached.
If the data cache line is dirty, write the line back to memory. A cache line is dirty when one or
more words of the cache line have been modified by the processor, but are not yet written to
memory.
Clear the valid bit for the line.
23
22
21
20
8–52,
19
18
“initd initialize data cache line” on page
17
for other cache-clearing options.
16
15
IMM16
14
13
12
Cache and Tightly Coupled Memory
11
10
9
“flushda flush data cache
8
Nios II Processor Reference Handbook
8–55, and
flush data cache line
7
6
5
“initda initialize data
4
0x3b
3
chapter of
2
1
8–51
0