IPR-NIOS Altera, IPR-NIOS Datasheet - Page 86

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–40
Nios II Processor Reference Handbook
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1
Illegal Instruction
Illegal instructions are instructions with an undefined opcode or opcode-extension
field. The Nios II processor can check for illegal instructions and generate an
exception when an illegal instruction is encountered. When your system contains an
MMU or MPU, illegal instruction checking is always on. When no MMU or MPU is
present, you have the option to have the processor check for illegal instructions.
To see how to control this option, refer to the
Builder
When the processor issues an instruction with an undefined opcode or
opcode-extension field, and illegal instruction exception checking is turned on, an
illegal instruction exception is generated.
Refer to the OP Encodings and OPX Encodings for R-Type Instructions tables in the
Instruction Set Reference
unused opcodes and opcode extensions.
All undefined opcodes are reserved. The processor does occasionally use some
undefined encodings internally. Executing one of these undefined opcodes does not
trigger an illegal instruction exception. Refer to the
chapter of the Nios II Processor Reference Handbook for details on each specific Nios II
core.
Supervisor-only Instruction
When your system contains an MMU or MPU and the processor is in user mode
(status.U = 1), executing a supervisor-only instruction results in a supervisor-only
instruction exception. The supervisor-only instructions are initd, initi, eret, bret,
rdctl, and wrctl.
This exception is implemented only in Nios II processors configured to use supervisor
mode and user mode. Refer to
Supervisor-only Instruction Address
When your system contains an MMU and the processor is in user mode (status.U =
1), attempts to access a supervisor-only instruction address result in a supervisor-only
instruction address exception. Any instruction fetch can cause this exception. For
definitions of supervisor-only address ranges, refer to
This exception is implemented only in Nios II processors that include the MMU.
Supervisor-only Data Address
When your system contains an MMU and the processor is in user mode (status.U =
1), any attempt to access a supervisor-only data address results in a supervisor-only
data address exception. Instructions that can cause a supervisor-only data address
exception are all loads, all stores, and flushda.
This exception is implemented only in Nios II processors that include the MMU.
chapter of the Nios II Processor Reference Handbook.
chapter of the Nios II Processor Reference Handbook to see the
“Operating Modes” on page 3–1
Instantiating the Nios II Processor in SOPC
Nios II Core Implementation Details
Table 3–2 on page
December 2010 Altera Corporation
Chapter 3: Programming Model
for more information.
Exception Processing
3–4.