IPR-NIOS Altera, IPR-NIOS Datasheet - Page 34

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–12
Figure 2–2. Nios II Memory and I/O Organization
Nios II Processor Reference Handbook
Nios II Processor Core
Instruction and Data Buses
Program
Purpose
Register
Counter
General
File
f
Figure 2–2
processor core.
The Nios II architecture supports separate instruction and data buses, classifying it as
a Harvard architecture. Both the instruction and data buses are implemented as
Avalon-MM master ports that adhere to the Avalon-MM interface specification. The
data master port connects to both memory and peripheral components, while the
instruction master port connects only to memory components.
Refer to the
Instruction
Selector
Selector
Logic
Logic
Data
Bus
Bus
shows a diagram of the memory and I/O organization for a Nios II
Avalon Interface Specifications
Bypass
MPU Instruction Regions
Cache
Logic
Data
MPU Data Regions
Lookaside Buffer
Translation
MMU
Instruction
Cache
Cache
Data
M
S
Avalon Master Port
Avalon Slave Port
for details of the Avalon-MM interface.
M
M
M
M
M
M
Tightly Coupled
Tightly Coupled
Tightly Coupled
Tightly Coupled
Instruction
Instruction
Memory N
Memory N
Memory 1
Memory 1
Data
Data
Avalon System
Interconnect
Fabric
December 2010 Altera Corporation
Chapter 2: Processor Architecture
Memory and I/O Organization
S
S
Peripheral
Memory
Slave