IPR-NIOS Altera, IPR-NIOS Datasheet - Page 257
IPR-NIOS
Manufacturer Part Number
IPR-NIOS
Description
IP NIOS II MEGACORE RENEW
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-NIOS.pdf
(294 pages)
Specifications of IPR-NIOS
License
Renewal License
Lead Free Status / RoHS Status
Not applicable / Not applicable
- Current page: 257 of 294
- Download datasheet (3Mb)
Chapter 8: Instruction Set Reference
Instruction Set Reference
muli
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
A
28
27
26
25
24
B
rB ← (rA × σ(IMM16))
muli rB, rA, IMM16
muli r6, r7, -100
Sign-extends the 16-bit immediate value IMM16 to 32 bits and multiplies it by the value of rA.
Stores the 32 low-order bits of the product to rB. The result is independent of whether rA is
treated as a signed or unsigned number.
Nios II processors that do not implement the muli instruction cause an unimplemented
instruction exception.
Carry Detection and Overflow Detection:
For a discussion of carry and overflow detection, refer to the mul instruction.
Unimplemented instruction
I
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
23
22
21
20
19
18
31..0
17
16
15
IMM16
14
13
12
11
10
9
8
Nios II Processor Reference Handbook
7
multiply immediate
6
5
4
0x24
3
2
1
8–71
0
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